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Merge pull request #43 from jerryz123/improvements
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Improve naming | update to latest spike
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ksco authored Aug 9, 2024
2 parents caae5c8 + bdae5ab commit 0f188dd
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3 changes: 2 additions & 1 deletion .github/workflows/build-and-test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ jobs:
run: |
git clone https://github.com/riscv-software-src/riscv-isa-sim.git
cd riscv-isa-sim
git reset --hard 3a53c80ade3336b1d46c9db3a6c6be8311c32cc5
git reset --hard 91793ed7d964aa0031c5a9a31fa05ec3d11b3b0f
mkdir build
cd build
../configure --prefix=${{ github.workspace }}/riscv
Expand All @@ -55,6 +55,7 @@ jobs:
run: |
export PATH="${{ github.workspace }}/riscv/bin:$PATH"
export RISCV="${{ github.workspace }}/riscv"
make generate-stage1
make all -j4
- name: Archive artifacts
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9 changes: 6 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
##
##Usage: make all -j$(nproc) --environment-overrides [OPTIONS]
##
##Example: to generate isa=rv32gcv varch=vlen:128,elen:32 mode=machine tests, use:
##Example: to generate isa=rv32gcv_zvl128b_zve32f mode=machine tests, use:
## make all --environment-overrides VLEN=128 XLEN=32 MODE=machine -j$(nproc)
##
##Subcommands:
Expand Down Expand Up @@ -60,6 +60,9 @@ MABI = lp64d

ifeq ($(XLEN), 32)
MABI = ilp32f
VARCH = zvl${VLEN}b_zve32f
else
VARCH = zvl${VLEN}b_zve64d
endif

RISCV_PREFIX = riscv64-unknown-elf-
Expand Down Expand Up @@ -127,7 +130,7 @@ patching-stage2: build-patcher-spike compile-stage1
$(MAKE) $(tests_patch)

$(tests_patch):
LD_LIBRARY_PATH=$(SPIKE_INSTALL)/lib ${PATCHER_SPIKE} --isa=${MARCH} --varch=vlen:${VLEN},elen:${XLEN} $(PK) ${OUTPUT_STAGE1_BIN}$(shell basename $@ .patch) > ${OUTPUT_STAGE2_PATCH}$@
LD_LIBRARY_PATH=$(SPIKE_INSTALL)/lib ${PATCHER_SPIKE} --isa=${MARCH}_${VARCH} $(PK) ${OUTPUT_STAGE1_BIN}$(shell basename $@ .patch) > ${OUTPUT_STAGE2_PATCH}$@

generate-stage2: patching-stage2
build/merger -stage1output ${OUTPUT_STAGE1} -stage2output ${OUTPUT_STAGE2} -stage2patch ${OUTPUT_STAGE2_PATCH}
Expand All @@ -140,7 +143,7 @@ tests_stage2 = $(addsuffix .stage2, $(tests))

$(tests_stage2):
$(RISCV_GCC) -march=${MARCH} -mabi=${MABI} $(RISCV_GCC_OPTS) $(STAGE2_GCC_OPTS) -I$(ENV) -Imacros/general -T$(ENV)/link.ld $(ENV_CSRCS) ${OUTPUT_STAGE2}$(shell basename $@ .stage2).S -o ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)
${SPIKE} --isa=${MARCH} --varch=vlen:${VLEN},elen:${XLEN} $(PK) ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)
${SPIKE} --isa=${MARCH}_${VARCH} $(PK) ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)


clean-out:
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