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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.9k 591

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.2k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 203

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 322

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 812 220

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 721 176

Repositories

Showing 10 of 107 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 246 Apache-2.0 74 20 8 Updated Oct 3, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,936 Apache-2.0 591 308 (1 issue needs help) 159 Updated Oct 3, 2024
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 3 Apache-2.0 1 0 0 Updated Oct 3, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 65 Apache-2.0 36 66 9 Updated Oct 3, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 53 Apache-2.0 39 89 53 Updated Oct 3, 2024
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,335 203 468 (15 issues need help) 26 Updated Oct 3, 2024
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 6 Apache-2.0 2 11 1 Updated Oct 3, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 112 Apache-2.0 21 17 24 Updated Oct 3, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 160 Apache-2.0 21 65 8 Updated Oct 3, 2024
  • chisel-nix Public

    Nix scripts used to manage the chisel projects.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 24 1 0 0 Updated Oct 3, 2024
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