Add initial compile support for RISC V #95
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aimixsaka
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Dec 5, 2023
- Fix broken cargo target - Use forked repo to support riscv: https://github.com/aimixsaka/nih-plug/tree/riscv - Upstreamed: robbert-vdh/nih-plug#95
aimixsaka
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Dec 5, 2023
- Fix broken cargo target - Use forked repo to support riscv: https://github.com/aimixsaka/nih-plug/tree/riscv_backport - Upstreamed: robbert-vdh/nih-plug#95
This was referenced Dec 5, 2023
felixonmars
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Dec 5, 2023
- Fix broken cargo target - Use forked repo to support riscv: https://github.com/aimixsaka/nih-plug/tree/riscv - Upstreamed: robbert-vdh/nih-plug#95
felixonmars
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Dec 5, 2023
- Fix broken cargo target - Use forked repo to support riscv: https://github.com/aimixsaka/nih-plug/tree/riscv_backport - Upstreamed: robbert-vdh/nih-plug#95
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Thanks! The only other place that's instruction set-dependent is the FTZ handling. Do you happen to know if there's any standard way to enable FTZ on RISC-V? |
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This pr add initial compilation support for RISC V 64.
Tested on
riscv64 qemu userandSophgo Mango rv64imafdc