TriggerDmode case fail，when accessing 8-9 trigger

[zhajio1988]

our riscv core vendor specify that tselect.index 0-7 can only be mcontrol, 8-9 can only be one of icount/ietrigger.
TriggerDmode case trigger.S traverses the index from 0-9, and the type selected is 2, at this time, icount and itrigger, etrigger can only be accessed when the type is equal to 3,4,5, which leads to an error at tselect.index 8. How to deal with the situation?
Shouldn't we read the value of tinfo when we write tselect and then decide the value of a0?
li a0, (2<<60) | (2<<28) | (1<<6) | (1<<1)

[en-sc]

icount and itrigger, etrigger can only be accessed when the type is equal to 3,4,5, which leads to an error at tselect.index 8.

Do you mean writing tdata1 with tdata1.type == 2 while tselect is 8 causes an illegal instruction exception on your HW?
This behavior is prohibited by the spec, namely [Chapter 5. Sdtrig (ISA Extension)] (The RISC-V Debug
Specification, Version 1.0.0-rc3):

M-Mode and Debug Mode accesses to trigger CSRs that are used by any of the implemented triggers must succeed, regardless of the current type of the currently selected trigger.

However, the implementation of write_store_trigger has some flaws, e.g. write_triggers should disable the trigger by writing tdata1 = 0 before writing tdata2 (see [5.7. Trigger Module Registers]).

riscv-tests/debug/programs/trigger.S

Lines 66 to 78 in b0eb63a

	write_triggers:
	// a0: value to write to each tdata1
	// a1: value to write to each tdata2
	li t0, 0
	2:
	csrw CSR_TSELECT, t0
	csrr t1, CSR_TSELECT
	bne t0, t1, 1f
	addi t0, t0, 1
	csrw CSR_TDATA2, a1
	csrw CSR_TDATA1, a0
	j 2b
	1: ret

[zhajio1988]

@en-sc
Do you mean writing tdata1 with tdata1.type == 2 while tselect is 8 causes an illegal instruction exception on your HW?
Yes, it is.