Change DTM IDCODE from SiFive HiFive1's 0x10e31913 to Spike's 0xdeadb…

…eef (#565)
riscv-software-src · Jun 27, 2024 · b0eb63a · b0eb63a
1 parent 74c9c14
commit b0eb63a
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Showing 4 changed files with 5 additions and 5 deletions.
diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
@@ -5,7 +5,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME $_CHIPNAME.cpu
 if {$::env(USE_FREERTOS)} {

diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME_0 $_CHIPNAME.cpu0
 set _TARGETNAME_1 $_CHIPNAME.cpu1

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
@@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
 set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef
 
 set _TARGETNAME_0 $_CHIPNAME.cpu0
 set _TARGETNAME_1 $_CHIPNAME.cpu1

diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg
@@ -5,8 +5,8 @@ adapter driver remote_bitbang
 remote_bitbang host $::env(REMOTE_BITBANG_HOST)
 remote_bitbang port $::env(REMOTE_BITBANG_PORT)
 
-jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913
-jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap riscv.0 cpu -irlen 5 -expected-id 0xdeadbeef
+jtag newtap riscv.1 cpu -irlen 5 -expected-id 0xdeadbeef
 
 target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0
 target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1