vector: disassemble: Let operand ordering be vd, [vrf]s1, vs2 to vector multiply-add instructions

[YenHaoChen]

Vector integer multiply-add instructions have a different assembly format to others. Specifically, the operand ordering of these instructions is rd, [vr]s1, vs2, while one of the others is rd, vs2, [vr]s1. (I was wondering whether this is a bug to the spec. Please correct me if I am wrong about this.)

[aswaterman]

The spec is correct; see this NOTE: https://github.com/riscv/riscv-isa-manual/blob/8b9dc50e562af27c9ab22ae0a2d3bf528c6bd41d/src/v-st-ext.adoc#L2264-L2268

However, I think your fix is incomplete. It includes only integer instructions.

You also need the single-width floating-point FMAs: https://github.com/riscv/riscv-isa-manual/blob/8b9dc50e562af27c9ab22ae0a2d3bf528c6bd41d/src/v-st-ext.adoc#L3331-L3362

And the widening floating-point FMAs: https://github.com/riscv/riscv-isa-manual/blob/8b9dc50e562af27c9ab22ae0a2d3bf528c6bd41d/src/v-st-ext.adoc#L3376-L3390

I believe that is all.

[YenHaoChen]

@aswaterman Thank you for the review. I revised the PR and made the following changes.

• Breakdown the commit by instruction group from the debug spec, i.e., splitting d398872 into ff62109 and 7f38a50.
• Let operand ordering be vd, [vf]s1, vs2 to vector floating-point fused multiply-add instructions, i.e., adding b47d0ba and 6a1a5db.

[aswaterman]

LGTM now, thanks.

[aswaterman]

@YenHaoChen I sent you a github invite with write permissions so that you can directly participate in PR reviews (and so that you can merge your own PRs once they're approved).

[YenHaoChen]

@aswaterman Thank you.