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Fix mcontrol6 mask low/high operations. #1771

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merged 1 commit into from
Aug 19, 2024

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rtwfroody
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I doubt this code was ever tested, and this change isn't tested either, because OpenOCD doesn't use this trigger type.

This problem was reported in
riscv/riscv-debug-spec#1057

@rtwfroody
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@YenHaoChen, can you review this?

@YenHaoChen
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The old code was from the 0.13 version, and the patch provides the behavior of the ratified version. After the patch, the code makes more sense to me.

Reference:
image

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@aswaterman I think this change is good to go.

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I think we need reg_t(1).

(Sorry that I forget to submit the review.)

Comment on lines 199 to 200
reg_t tdata2_low = tdata2 & ((1 << (xlen/2)) - 1);
reg_t value_low = value & ((1 << (xlen/2)) - 1);
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I think we need reg_t(1).

        reg_t tdata2_low = tdata2 & ((reg_t(1) << (xlen/2)) - 1);
        reg_t value_low = value & ((reg_t(1) << (xlen/2)) - 1);

reg_t mask = tdata2 >> (xlen/2);
return ((value >> (xlen/2)) & mask) == (tdata2 & mask);
reg_t tdata2_high = tdata2 >> (xlen/2);
reg_t tdata2_low = tdata2 & ((1 << (xlen/2)) - 1);
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I think we need reg_t(1).

        reg_t tdata2_low = tdata2 & ((reg_t(1) << (xlen/2)) - 1);

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I think @YenHaoChen is right about the out-of-bounds shifts by 32 when int is 32 bits. Ping me again when that's done and I'll merge.

I doubt this code was ever tested, and this change isn't tested either,
because OpenOCD doesn't use this trigger type.

This problem was reported in
riscv/riscv-debug-spec#1057
@rtwfroody
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I've added reg_t() where necessary. Thanks.

@aswaterman aswaterman merged commit a8c9d9c into riscv-software-src:master Aug 19, 2024
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3 participants