AIA: Implement Smaia/Ssaia extension #1635
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
YenHaoChen
changed the title
YenHaoChen
force-pushed
the
pr-aia
branch
9 times, most recently
from
62c78b2
to
88d616f
Compare
YenHaoChen
force-pushed
the
pr-aia
branch
4 times, most recently
from
a9a619e
to
a379dd1
Compare
YenHaoChen
force-pushed
the
pr-aia
branch
2 times, most recently
from
2354478
to
ae57784
Compare
YenHaoChen
changed the title
YenHaoChen
force-pushed
the
pr-aia
branch
3 times, most recently
from
2a56593
to
75b448e
Compare
YenHaoChen
force-pushed
the
pr-aia
branch
6 times, most recently
from
4d594ea
to
88c443c
Compare
YenHaoChen
force-pushed
the
pr-aia
branch
2 times, most recently
from
4f0b843
to
9e02c6d
Compare
All bytes of the supervisor-level iprio array are read-only 0s, and stopi.IPRIO is always 1 whenever stopi is not 0.
…and hviprio2h CSRs)
AIA introduces the concept of inaccessible CSR, where accessing from M-mode or HS-mode raises an illegal instruction exception, but doing so from VS-mode or VU-mode raises a virtual instruction exception. Without IMSIC, mtopei and stopei do not exist. In contrast, vstopei is an inaccessible CSR even without IMSIC, i.e., exits and is HS-qualified. In summary, accessing stopei from M-mode or HS-mode (v=0) raises illegal instruction, and accessing stopei (actually vstopei) from VS-mode or VU-mode (v=1) raises virtual instruction.
The pair hvictl.IID=9 and hvictl.IPRIO=0 generally represent no interrupt in hvictl. While zeroing also signifies no interrupt, this intermediate commit in the AIA series aims to explicitly state the absence of an interrupt condition to prevent confusion in subsequent intermediate commits.
…al_permission_csr_t
… or siph) from VS-mode when hvictl.VTI=1
…ph) from VS-mode when hvictl.VTI=1
If hvictl.VTI=0, vstopi returns information about the highest-priority pending-and-enabled major interrupt indicated by vsip and vsie. If hvictl.VTI=1, vstopi return information about a supervisor extenal interrupt if bit 9 is one in both vsip and vsie.
If hvictl.VTI=1, there are two interrupt candidates for VS level. One is a supervisor extenal interrupt if bit 9 is one in both vsip and vsie. The other one is specified by hvictl.IID if hvictl.IID is not 9. The hvictl.DPR determines the priority order between two interrupts.
If hvictl.IPRIOM=1, vstopi.IPRIO indicates the priority of the highest-priority interrupt if vstopi is nonzero. For a supervisor external interrupt, vstopi.IPRIO is hvictl.IPRIO if hvictl.IID=9 and hvictl.IPRIO!=0; otherwise, vstopi.IPRIO is 255. For other interrupts under hvictl.VTI=1, vstopi.IPRIO is 0 if hvictl.iprio=0 and hvictl.dpr=0; vstopi.IPRIO is hvictl.iprio if hvictl.iprio!=0; vstopi.IPRIO is 255 if hvictl.iprio=0 and hvictl.dpr=1. For other interrupts under hvictl.VTI=0, vstopi.IPRIO is 255 (lowest priority). That is because other interrupts have the same priority value 0 due to hviprio1=hviprio2=0. In other words, the hvictl.IPRIO of other interrupts is determined by the default priority, which is lower than the SEI with the lowest priority value 255.
… in mideleg remain 0s (interrupt filtering) The modification is backward compatible because mvien is implicitly 0 without AIA.
An interrupt is pending at VS level if and only if vstopi is not 0. The modification is backward compatible because hvictl is implicitly 0 without AIA.
… hviprio[12](h), and supervisor-level iprio array
…, (v)sieh, hidelegh, and hviph
|
@aswaterman @jerryz123 It has been months. I give this PR a rebase. Can someone review this PR? |
|
The CI shows some issues with the jtag scan and fetching registers. I need help understanding the message. |
|
I don’t have time to do a good job reviewing such a large PR this week. I’d like to help, but it might be a while before I can spare the time. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR aims to provide a minimal required (recommended) implementation for the AIA extension. There is no APLIC/IMSIC device in this PR. The hstatus.VGEIN is read-only 0. The ipiro arrays and hviprio1/hviprio2 are also read-only 0. The AIA specification allows these behaviors. Nevertheless, I am willing to provide enhancements for these features if desired.