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mcontrol/mcontrol6 on CBO #1413

Merged
merged 3 commits into from
Jul 19, 2023
Merged

mcontrol/mcontrol6 on CBO #1413

merged 3 commits into from
Jul 19, 2023

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YenHaoChen
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@YenHaoChen YenHaoChen commented Jul 13, 2023 •
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This PR fixes two mcontrol/mcontrol6 trigger issues on cbo instructions.

  1. The tval should capture the effective address when a (trigger) exception on cbo.zero. (*TVAL should capture the effective address on an exception riscv/riscv-isa-manual#1317). The previous implementation does not pass the effective address on checking_triggers(). This PR proposes extending the checking_triggers() with an additional parameter "tval" and passing the effective address.
  2. The mcontrol/mcontrol6 trigger must match cbo.clean/inval as stores. This PR checks all addresses in the cache block appointed by the cbo instruction.

@YenHaoChen YenHaoChen changed the title Pr mcontrol cbo zero tval The xtval should capture the effective address on a (trigger) exception Jul 13, 2023
@YenHaoChen YenHaoChen changed the title The xtval should capture the effective address on a (trigger) exception The xtval should capture the effective address when a (trigger) exception on cbo.zero Jul 13, 2023
@aswaterman
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@scottj97 may we rely on you to run this one through your internal debug tests?

@YenHaoChen
mcontrol/mcontrol6 triggers on cbo.flush/clean
8658429 
The mcontrol/mcontrol6 store address before has a higher priority over page
faults and access faults. Thus, trigger checking should before the translate().

This commit checks all address of the cache block.

Reference: Debug spec 1.0, 5.5.3 Cache Operations
Reference: CMO spec 1.0.1, 2.5.4 Breakpoint Exceptions and Debug Mode Entry
@YenHaoChen YenHaoChen mentioned this pull request Jul 19, 2023
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@YenHaoChen YenHaoChen changed the title The xtval should capture the effective address when a (trigger) exception on cbo.zero mcontrol/mcontrol6 on CBO Jul 19, 2023
scottj97
scottj97 approved these changes Jul 19, 2023
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I don't have any coverage of CBO instructions, but this doesn't seem to break anything else.

@aswaterman aswaterman merged commit 432c9ee into riscv-software-src:master Jul 19, 2023
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@scottj97 scottj97 scottj97 approved these changes

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@YenHaoChen @aswaterman @scottj97