Skip to content

Commit

Permalink
Only implement one solution for native triggers.
Browse files Browse the repository at this point in the history
When S-mode is present, use option 1 (disable triggers in M-mode unless
MIE is set) from the Debug Spec. When S-mode is not present, use option
2 (implement mte and mpte bits in tcontrol).

See discussion in #1777.
  • Loading branch information
rtwfroody committed Sep 5, 2024
1 parent 4abd669 commit e0ebf31
Show file tree
Hide file tree
Showing 2 changed files with 23 additions and 12 deletions.
5 changes: 3 additions & 2 deletions riscv/csr_init.cc
Original file line number Diff line number Diff line change
Expand Up @@ -205,13 +205,14 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa)
add_csr(CSR_TDATA2, tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2));
add_csr(CSR_TDATA3, std::make_shared<tdata3_csr_t>(proc, CSR_TDATA3));
add_csr(CSR_TINFO, std::make_shared<tinfo_csr_t>(proc, CSR_TINFO));
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
if (!proc->extension_enabled_const('S')) {
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<masked_csr_t>(proc, CSR_TCONTROL, CSR_TCONTROL_MPTE | CSR_TCONTROL_MTE, 0));
}
} else {
add_csr(CSR_TDATA1, std::make_shared<const_csr_t>(proc, CSR_TDATA1, 0));
add_csr(CSR_TDATA2, tdata2 = std::make_shared<const_csr_t>(proc, CSR_TDATA2, 0));
add_csr(CSR_TDATA3, std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0));
add_csr(CSR_TINFO, std::make_shared<const_csr_t>(proc, CSR_TINFO, 0));
add_csr(CSR_TCONTROL, tcontrol = std::make_shared<const_csr_t>(proc, CSR_TCONTROL, 0));
}
unsigned scontext_length = (xlen == 32 ? 16 : 32); // debug spec suggests 16-bit for RV32 and 32-bit for RV64
add_supervisor_csr(CSR_SCONTEXT, scontext = std::make_shared<masked_csr_t>(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0));
Expand Down
30 changes: 20 additions & 10 deletions riscv/triggers.cc
Original file line number Diff line number Diff line change
Expand Up @@ -66,8 +66,7 @@ bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const
auto state = proc->get_state();
auto prv = use_prev_prv ? state->prev_prv : state->prv;
auto v = use_prev_prv ? state->prev_v : state->v;
auto m_enabled = get_action() != 0 || (tcontrol_value(state) & CSR_TCONTROL_MTE);
return (prv < PRV_M || m_enabled) && mode_match(prv, v) && textra_match(proc);
return (prv < PRV_M) && mode_match(prv, v) && textra_match(proc);
}

bool trigger_t::mode_match(reg_t prv, bool v) const noexcept
Expand Down Expand Up @@ -121,14 +120,25 @@ bool trigger_t::allow_action(processor_t * const proc) const
{
const state_t *state = proc->get_state();
if (get_action() == ACTION_DEBUG_EXCEPTION) {
const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
return (state->prv != PRV_M || mstatus_mie) &&
(state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) &&
(state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie);
if (proc->extension_enabled('S')) {
// The hardware prevents triggers with action=0 from matching or firing
// while in M-mode and while MIE in mstatus is 0. If medeleg [3]=1 then it
// prevents triggers with action=0 from matching or firing while in S-mode
// and while SIE in sstatus is 0. If medeleg [3]=1 and hedeleg [3]=1 then
// it prevents triggers with action=0 from matching or firing while in
// VS-mode and while SIE in vstatus is 0.
const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE;
const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE;
const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE;
const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1;
const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1;
return (state->prv != PRV_M || mstatus_mie) &&
(state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) &&
(state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie);
} else {
// mte and mpte in tcontrol is implemented. medeleg [3] is hard-wired to 0.
return (state->prv != PRV_M) || (tcontrol_value(state) & CSR_TCONTROL_MTE);
}
}
return true;
}
Expand Down

0 comments on commit e0ebf31

Please sign in to comment.