Merge pull request #1760 from YenHaoChen/pr-mxr

Let MXR not affect implicit memory access for VS-stage address translation
riscv-software-src · Aug 5, 2024 · 1b53bf9 · 1b53bf9
2 parents 2890ea7 + e749bb0
commit 1b53bf9
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
@@ -404,7 +404,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
   int maxgpabits = vm.levels * vm.idxbits + vm.widenbits + PGSHIFT;
   reg_t maxgpa = (1ULL << maxgpabits) - 1;
 
-  bool mxr = proc->state.sstatus->readvirt(false) & MSTATUS_MXR;
+  bool mxr = !is_for_vs_pt_addr && (proc->state.sstatus->readvirt(false) & MSTATUS_MXR);
   // tinst is set to 0x3000/0x3020 - for RV64 read/write respectively for
   // VS-stage address translation (for spike HSXLEN == VSXLEN always) else
   // tinst is set to 0x2000/0x2020 - for RV32 read/write respectively for