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Avoid Module creation for Constant Gate scenarios #481

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Avoid Module creation for Constant Gate scenarios #481

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292bf2d
Avoid Module creation for Constant Gate scenarios
mjayasim9 Apr 5, 2024
81734f2
Removed extra import
mjayasim9 Apr 5, 2024
efa4b95
Added changes based on comments
mjayasim9 Apr 8, 2024
7a3974a
Merge branch 'main' of https://github.com/mjayasim9/rohd into ConstGates
mjayasim9 Jun 18, 2024
cbf0c26
Merge branch 'intel:main' into ConstGates
mjayasim9 Jul 9, 2024
8e7789b
Added fixes based on feedback
mjayasim9 Jul 9, 2024
abb0d87
Merge branch 'main' of https://github.com/mjayasim9/rohd into ConstGates
mjayasim9 Jul 9, 2024
4393d10
Merge branch 'ConstGates' of https://github.com/mjayasim9/rohd into C…
mjayasim9 Jul 9, 2024
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52 changes: 49 additions & 3 deletions lib/src/signals/logic.dart
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Original file line number Diff line number Diff line change
Expand Up @@ -319,13 +319,59 @@ class Logic {
void operator <=(Logic other) => gets(other);

/// Logical bitwise NOT.
Logic operator ~() => NotGate(this).out;
Logic operator ~() {
if (this is Const) {
if (value.isValid) {
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I think we can rely on the operators within LogicValue for this? i.e. something like Const(~this.value)?

if (value == LogicValue.of(0, width: width)) {
return Const(LogicValue.filled(width, LogicValue.one));
} else if (value == LogicValue.filled(width, LogicValue.one)) {
return Const(LogicValue.of(0, width: width));
}
} else {
return Const(LogicValue.x, width: width);
}
}
return NotGate(this).out;
}

/// Logical bitwise AND.
Logic operator &(Logic other) => And2Gate(this, other).out;
Logic operator &(Logic other) {
if (this is Const || other is Const) {
if (value.isValid && other.value.isValid) {
if (value == LogicValue.of(0, width: width) ||
other.value == LogicValue.of(0, width: width)) {
return Const(LogicValue.of(0, width: width));
} else if (value == LogicValue.filled(width, LogicValue.one)) {
return other;
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What if other is Const and this is not Const but has a value of all 1s currently? Need to be cautious to only consider the value if it's a Const.

} else if (other.value == LogicValue.filled(width, LogicValue.one)) {
return this;
}
} else {
return Const(LogicValue.x, width: width);
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This isn't quite right, consider 11x11 & 11111 == 11x11

If we just cover the cases of all 0's and all 1's that's probably enough and let the rest fall through to the and gate?

}
}
return And2Gate(this, other).out;
}

/// Logical bitwise OR.
Logic operator |(Logic other) => Or2Gate(this, other).out;
Logic operator |(Logic other) {
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same here for or

if (this is Const || other is Const) {
if (value.isValid && other.value.isValid) {
if (value == LogicValue.filled(width, LogicValue.one) ||
other.value == LogicValue.filled(width, LogicValue.one)) {
return Const(LogicValue.filled(width, LogicValue.one));
} else if (value == LogicValue.of(LogicValue.zero, width: width)) {
return other;
} else if (other.value ==
LogicValue.of(LogicValue.zero, width: width)) {
return this;
}
} else {
return Const(LogicValue.x, width: width);
}
}
return Or2Gate(this, other).out;
}

/// Logical bitwise XOR.
Logic operator ^(Logic other) => Xor2Gate(this, other).out;
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103 changes: 103 additions & 0 deletions test/gate_test.dart
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Expand Up @@ -353,6 +353,109 @@ void main() {
});
});

group('Const input Gate test', () {
test('NotGate single bit Constant input', () async {
final a = Logic();
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naming the variables could be helpful for understanding the intent of the test, e.g. normalLogic, const0, etc.

final b = Const(LogicValue.zero, width: 1);
final c = Const(LogicValue.x, width: 1);
final d = Const(LogicValue.one, width: 1);
a.put(LogicValue.one);

final result = ~b;
expect(result, isA<Const>());
expect(result.value, equals(LogicValue.one));

final result2 = ~c;
expect(result2, isA<Const>());
expect(result2.value, equals(LogicValue.x));

final result3 = ~d;
expect(result3, isA<Const>());
expect(result3.value, equals(LogicValue.zero));
});

test('NotGate Multi bit Constant input', () async {
final b = Const(bin('1111'), width: 4);
final c = Const(bin('0100'), width: 4);
final result = ~b;

expect(result, isA<Const>());
expect(result.value, equals(LogicValue.of(LogicValue.zero, width: 4)));

final result2 = ~c;
expect(result2, isA<Logic>());
expect(result2.value, equals(LogicValue.of(11, width: 4)));
});

test('And2Gate Single bit Constant input', () async {
final a = Logic();
final b = Const(LogicValue.zero, width: 1);
final c = Const(LogicValue.x, width: 1);
final d = Const(LogicValue.one, width: 1);
a.put(LogicValue.one);

final result = a & b;
expect(result, isA<Const>());
expect(result.value, equals(LogicValue.zero));

final result2 = a & c;
expect(result2, isA<Const>());
expect(result2.value, equals(LogicValue.x));

final result3 = a & d;
expect(result3, isA<Logic>());
expect(result3.value, equals(a.value));
});

test('And2Gate Multi bit Constant input', () async {
final a = Const(LogicValue.of(LogicValue.zero, width: 4));
final b = Const(bin('1111'), width: 4);
final c = Const(bin('0100'), width: 4);
final result = a & c;

expect(result, isA<Const>());
expect(result.value, equals(LogicValue.of(LogicValue.zero, width: 4)));

final result2 = b & c;
expect(result2, isA<Logic>());
expect(result2.value, equals(c.value));
});

test('OR2Gate Single bit Constant input', () async {
final a = Logic();
final b = Const(LogicValue.zero, width: 1);
final c = Const(LogicValue.x, width: 1);
final d = Const(LogicValue.one, width: 1);
a.put(LogicValue.one);

final result = a | b;
expect(result, isA<Logic>());
expect(result.value, equals(a.value));

final result2 = a | c;
expect(result2, isA<Const>());
expect(result2.value, equals(LogicValue.x));

final result3 = a | d;
expect(result3, isA<Const>());
expect(result3.value, equals(LogicValue.one));
});

test('OR2Gate Multi bit Constant input', () async {
final a = Const(LogicValue.of(LogicValue.zero, width: 4));
final b = Const(bin('1111'), width: 4);
final c = Const(bin('0100'), width: 4);
final result = a | c;

expect(result, isA<Logic>());
expect(result.value, equals(c.value));

final result2 = b | c;
expect(result2, isA<Const>());
expect(result2.value, equals(LogicValue.filled(4, LogicValue.one)));
});
});

group('simcompare', () {
test('NotGate single bit', () async {
final gtm = GateTestModule(Logic(), Logic());
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