Gates should output X (never Z) when inputs are invalid

intel · Jul 20, 2023 · ed1eaca · ed1eaca
1 parent ad73088
commit ed1eaca
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Showing 4 changed files with 35 additions and 8 deletions.
diff --git a/lib/src/modules/conditional.dart b/lib/src/modules/conditional.dart
@@ -831,7 +831,14 @@ class ConditionalAssign extends Conditional {
       guard(driver);
     }
 
-    _receiverOutput.put(driverValue(driver));
+
+    final currentValue = driverValue(driver);
+    if (!currentValue.isValid ){
+        _receiverOutput.put(LogicValue.x);
+    }
+    else{
+       _receiverOutput.put(currentValue);
+    }
 
     if (!drivenSignals.contains(receiver) || receiver.value.isValid) {
       drivenSignals.add(receiver);
@@ -965,6 +972,12 @@ class Case extends Conditional {
       }
       return;
     }
+
+     for (final receiver in receivers) {
+        receiver.put(LogicValue.x);
+     }
+
+
 
     CaseItem? foundMatch;
 

diff --git a/lib/src/modules/gates.dart b/lib/src/modules/gates.dart
@@ -663,11 +663,11 @@ class Mux extends Module with InlineSystemVerilog {
   /// Executes the functional behavior of the mux.
   void _execute() {
     if (!_control.value.isValid) {
-      out.put(_control.value);
+      out.put(LogicValue.x);
     } else if (_control.value == LogicValue.zero) {
-      out.put(_d0.value);
+      out.put(_d0.value.isValid ? _d0.value : LogicValue.x);
     } else if (_control.value == LogicValue.one) {
-      out.put(_d1.value);
+      out.put(_d1.value.isValid ? _d1.value : LogicValue.x);
     }
   }
 

diff --git a/lib/src/utilities/simcompare.dart b/lib/src/utilities/simcompare.dart
@@ -81,7 +81,9 @@ class Vector {
         }
         return arrAssigns.toString();
       } else {
-        return '$signalName = ${inputValues[signalName]};';
+        final signalVal =
+            LogicValue.of(inputValues[signalName], width: signal.width);
+        return '$signalName = $signalVal;';
       }
     }).join('\n');
 

diff --git a/test/gate_test.dart b/test/gate_test.dart
@@ -258,13 +258,25 @@ void main() {
     test('Mux bus', () async {
       final mod = MuxWrapper(Logic(), Logic(width: 8), Logic(width: 8));
       await mod.build();
-      final vectors = [
+      final vector1 = [
         Vector({'control': 1, 'd0': 12, 'd1': 15}, {'y': 15}),
         Vector({'control': 0, 'd0': 18, 'd1': 7}, {'y': 18}),
         Vector({'control': 0, 'd0': 3, 'd1': 6}, {'y': 3}),
+        Vector({'control': 0, 'd0': 10, 'd1': LogicValue.z}, {'y': 10}),
+        Vector({'control': 1, 'd0': LogicValue.z, 'd1': 6}, {'y': 6}),
       ];
-      await SimCompare.checkFunctionalVector(mod, vectors);
-      final simResult = SimCompare.iverilogVector(mod, vectors);
+
+      final vector2 = [
+        Vector(
+            {'control': 1, 'd0': 6, 'd1': LogicValue.z}, {'y': LogicValue.x}),
+        Vector(
+            {'control': LogicValue.z, 'd0': 10, 'd1': 6}, {'y': LogicValue.x}),
+        Vector(
+            {'control': 0, 'd0': LogicValue.z, 'd1': 10}, {'y': LogicValue.x}),
+      ];
+
+      await SimCompare.checkFunctionalVector(mod, vector1 + vector2);
+      final simResult = SimCompare.iverilogVector(mod, vector1);
       expect(simResult, equals(true));
     });