Merge branch 'main' of https://github.com/mjayasim9/rohd into ConstGates

CHANGELOG.md

@@ -1,7 +1,7 @@
 ## Next release
 
 - Added `LogicNet`, `inOut`s, and `TriStateBuffer` to enable multi-directional wires, ports, and drivers.
-- Deprecated `CustomSystemVerilog` in favor of `SystemVerilog`, which has similar functionality but supports `inOut` ports and collapses all ports into a single `ports` argument.
+- Deprecated `CustomSystemVerilog` in favor of `SystemVerilog`, which has similar functionality but supports `inOut` ports, and collapses all ports into a single `ports` argument, as well as some other new features like custom definitions and parameter passthroughs.
 - Breaking: `ExternalSystemVerilogModule` and `InlineSystemVerilog` now extend `SystemVerilog` instead of `CustomSystemVerilog`, meaning the `instantiationVerilog` API arguments have been modified.
 - Breaking: Increased minimum Dart SDK version to 3.0.0.
 - Breaking: `Interface.connectIO` has an additional optional named argument for `inOutTags`.  Implementations of `Interface` which override `connectIO` will need to be updated.

analysis_options.yaml

@@ -36,7 +36,7 @@ linter:
     - avoid_function_literals_in_foreach_calls
     - avoid_implementing_value_types
     - avoid_init_to_null
-    # - avoid_js_rounded_ints
+    - avoid_js_rounded_ints
     - avoid_multiple_declarations_per_line
     - avoid_null_checks_in_equality_operators
     - avoid_positional_boolean_parameters
@@ -102,6 +102,7 @@ linter:
     - lines_longer_than_80_chars
     - literal_only_boolean_expressions
     - matching_super_parameters
+    - missing_code_block_language_in_doc_comment
     - missing_whitespace_between_adjacent_strings
     - no_adjacent_strings_in_list
     - no_default_cases
@@ -193,6 +194,7 @@ linter:
     - unnecessary_lambdas
     - unnecessary_late
     - unnecessary_library_directive
+    - unnecessary_library_name
     - unnecessary_new
     - unnecessary_null_aware_assignments
     - unnecessary_null_aware_operator_on_extension_on_nullable

lib/src/module.dart

@@ -418,6 +418,26 @@ abstract class Module {
           !isInOut(signal) &&
           subModule == null) {
         _addInternalSignal(signal);
+
+        // handle expanding the search for arrays
+        if (signal.parentStructure != null) {
+          await _traceInputForModuleContents(signal.parentStructure!,
+              dontAddSignal: dontAddSignal);
+          await _traceOutputForModuleContents(signal.parentStructure!,
+              dontAddSignal: signal.isPort);
+        }
+        if (signal is LogicStructure) {
+          for (final elem in signal.elements) {
+            await _traceInputForModuleContents(elem,
+                dontAddSignal: dontAddSignal);
+            await _traceOutputForModuleContents(elem,
+                dontAddSignal: signal.isPort);
+          }
+        }
+
+        for (final srcConnection in signal.srcConnections) {
+          await _traceOutputForModuleContents(srcConnection);
+        }
       }
 
       if (!dontAddSignal && isInput(signal)) {
@@ -515,6 +535,23 @@ abstract class Module {
           !isInOut(signal) &&
           subModule == null) {
         _addInternalSignal(signal);
+
+        // handle expanding the search for arrays
+        if (signal.parentStructure != null) {
+          await _traceOutputForModuleContents(signal.parentStructure!,
+              dontAddSignal: dontAddSignal);
+          await _traceInputForModuleContents(signal.parentStructure!,
+              dontAddSignal: signal.isPort);
+        }
+        if (signal is LogicStructure) {
+          for (final elem in signal.elements) {
+            await _traceOutputForModuleContents(elem,
+                dontAddSignal: dontAddSignal);
+            await _traceInputForModuleContents(elem,
+                dontAddSignal: signal.isPort);
+          }
+        }
+
         for (final dstConnection in signal.dstConnections) {
           await _traceInputForModuleContents(dstConnection);
         }
@@ -546,10 +583,6 @@ abstract class Module {
 
     _internalSignals.add(signal);
 
-    if (signal.isArrayMember) {
-      _addInternalSignal(signal.parentStructure!);
-    }
-
     // ignore: invalid_use_of_protected_member
     signal.parentModule = this;
   }
@@ -649,7 +682,7 @@ abstract class Module {
     )
       ..gets(x)
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _inputs[name] = inArr;
 
@@ -695,7 +728,7 @@ abstract class Module {
       naming: Naming.reserved,
     )
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _outputs[name] = outArr;
 
@@ -739,7 +772,7 @@ abstract class Module {
     )
       ..gets(x)
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _inOuts[name] = inOutArr;
 

lib/src/modules/bus.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // bus.dart
@@ -15,16 +15,16 @@ import 'package:rohd/rohd.dart';
 /// The output [subset] will have width equal to `|endIndex - startIndex| + 1`.
 class BusSubset extends Module with InlineSystemVerilog {
   /// Name for the input port of this module.
-  late final String _original;
+  late final String _originalName;
 
   /// Name for the output port of this module.
-  late final String _subset;
+  late final String _subsetName;
 
   /// The input to get a subset of.
-  late final Logic original = input(_original);
+  late final Logic _original = input(_originalName);
 
-  /// The output, a subset of [original].
-  late final Logic subset = output(_subset);
+  /// The output, a subset of [_original].
+  late final Logic subset = output(_subsetName);
 
   /// Start index of the subset.
   final int startIndex;
@@ -33,7 +33,7 @@ class BusSubset extends Module with InlineSystemVerilog {
   final int endIndex;
 
   @override
-  List<String> get expressionlessInputs => [_original];
+  List<String> get expressionlessInputs => [_originalName];
 
   /// Constructs a [Module] that accesses a subset from [bus] which ranges
   /// from [startIndex] to [endIndex] (inclusive of both).
@@ -55,13 +55,13 @@ class BusSubset extends Module with InlineSystemVerilog {
           ' than ${bus.width}');
     }
 
-    _original = Naming.unpreferredName('original_${bus.name}');
-    _subset =
+    _originalName = Naming.unpreferredName('original_${bus.name}');
+    _subsetName =
         Naming.unpreferredName('subset_${endIndex}_${startIndex}_${bus.name}');
 
-    addInput(_original, bus, width: bus.width);
+    addInput(_originalName, bus, width: bus.width);
     final newWidth = (endIndex - startIndex).abs() + 1;
-    addOutput(_subset, width: newWidth);
+    addOutput(_subsetName, width: newWidth);
 
     // so that people can't do a slice assign, not (yet?) implemented
     subset.makeUnassignable();
@@ -72,22 +72,22 @@ class BusSubset extends Module with InlineSystemVerilog {
   /// Performs setup steps for custom functional behavior.
   void _setup() {
     _execute(); // for initial values
-    original.glitch.listen((args) {
+    _original.glitch.listen((args) {
       _execute();
     });
   }
 
   /// Executes the functional behavior of this gate.
   void _execute() {
-    if (original.width == 1) {
-      subset.put(original.value);
+    if (_original.width == 1) {
+      subset.put(_original.value);
       return;
     }
 
     if (endIndex < startIndex) {
-      subset.put(original.value.getRange(endIndex, startIndex + 1).reversed);
+      subset.put(_original.value.getRange(endIndex, startIndex + 1).reversed);
     } else {
-      subset.put(original.value.getRange(startIndex, endIndex + 1));
+      subset.put(_original.value.getRange(startIndex, endIndex + 1));
     }
   }
 
@@ -99,13 +99,13 @@ class BusSubset extends Module with InlineSystemVerilog {
     if (inputs.length != 1) {
       throw Exception('BusSubset has exactly one input, but saw $inputs.');
     }
-    final a = inputs[_original]!;
+    final a = inputs[_originalName]!;
 
     assert(!a.contains(_expressionRegex),
         'Inputs to bus swizzle cannot contain any expressions.');
 
     // When, input width is 1, ignore startIndex and endIndex
-    if (original.width == 1) {
+    if (_original.width == 1) {
       return a;
     }
 

lib/src/modules/gates.dart

@@ -619,7 +619,7 @@ class LShift extends _ShiftGate {
 /// Performs a multiplexer/ternary operation.
 ///
 /// This is equivalent to something like:
-/// ```
+/// ```SystemVerilog
 /// control ? d1 : d0
 /// ```
 Logic mux(Logic control, Logic d1, Logic d0) => Mux(control, d1, d0).out;

lib/src/selection.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2024 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // selection.dart
@@ -21,7 +21,7 @@ extension IndexedLogic on List<Logic> {
   /// Alternatively we can approach this with `index.selectFrom(logicList)`
   ///
   /// Example:
-  /// ```
+  /// ```dart
   /// // ordering matches closer to array indexing with `0` index-based.
   /// List<Logic> logicList = [/* Add your Logic elements here */];
   /// selected <= logicList.selectIndex(index);

lib/src/signals/logic.dart

@@ -180,7 +180,7 @@ class Logic {
 
   /// Sets the value of [parentModule] to [newParentModule].
   ///
-  /// This should *only* be called by [Module.build()].  It is used to
+  /// This should *only* be called by [Module.build].  It is used to
   /// optimize search.
   @protected
   set parentModule(Module? newParentModule) {
@@ -846,7 +846,7 @@ class Logic {
   /// Alternatively we can approach this with `busList.selectIndex(index)`
   ///
   /// Example:
-  /// ```
+  /// ```dart
   /// // ordering matches closer to array indexing with `0` index-based.
   /// selected <= index.selectFrom(busList);
   /// ```

lib/src/signals/logic_array.dart

@@ -242,7 +242,7 @@ class LogicArray extends LogicStructure {
   /// to the length of the [updatedSubset].
   ///
   /// Example:
-  /// ```
+  /// ```dart
   /// LogicArray sampleLogic;
   /// // Note: updatedSubset.length < (sampleLogic.length - start)
   /// List<Logic> updatedSubset;

lib/src/signals/logic_structure.dart

@@ -251,7 +251,17 @@ class LogicStructure implements Logic {
         'Should only set parent module once.');
 
     _parentModule = newParentModule;
+  }
+
+  /// Performs a recursive call of setting [parentModule] on all of [elements]
+  /// and their [elements] for any sub-[LogicStructure]s.
+  @protected
+  void setAllParentModule(Module? newParentModule) {
+    parentModule = newParentModule;
     for (final element in elements) {
+      if (element is LogicStructure) {
+        element.setAllParentModule(newParentModule);
+      }
       element.parentModule = newParentModule;
     }
   }