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NUMA bindings support for private memory #82

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merged 1 commit into from
May 17, 2023

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vinser52
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@vinser52 vinser52 commented May 4, 2023

I think we can merge these changes to our develop branch while we are waiting for PR95 to be upstreamed.


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@vinser52 vinser52 requested review from igchor and byrnedj May 4, 2023 14:10
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byrnedj commented May 4, 2023

Thank you for the PR.

Do you think you could add in the forcePageAllocation method from PosixShmSegment.cpp, so that each page is prefaulted? See https://github.com/intel/CacheLib/blob/main/cachelib/shm/PosixShmSegment.cpp#L350.

This reduces the number of minor page faults dramatically (from over 1.7M down to ~100K).

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vinser52 commented May 4, 2023

Do you think you could add in the forcePageAllocation method from PosixShmSegment.cpp, so that each page is prefaulted? See https://github.com/intel/CacheLib/blob/main/cachelib/shm/PosixShmSegment.cpp#L350.

I think PR #81 should help in that case.

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:lgtm:

Reviewable status: 0 of 14 files reviewed, all discussions resolved (waiting on @byrnedj)

@byrnedj byrnedj merged commit fa8879c into intel:develop May 17, 2023
vinser52 added a commit that referenced this pull request Jul 17, 2023
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3 participants