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yosemite4n: linux-nuvoton: Add kernel driver patches
Summary: Add kernel driver patches that are still under upstream review. Test Plan: bitbake yosemite4n-image - Build Pass Signed-off-by: Marvin Lin <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,6 @@ | ||
| FILESEXTRAPATHS:prepend := "${THISDIR}/6.6:" | ||
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| LINUX_NUVOTON_PATCHES_INC ?= "" | ||
| LINUX_NUVOTON_PATCHES_INC:openbmc-fb-lf = "linux-patches-6.6.inc" | ||
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| include ${LINUX_NUVOTON_PATCHES_INC} |
89 changes: 89 additions & 0 deletions
89
...ernel/linux/linux-nuvoton/1000-dt-bindings-clock-npcm845-Add-reference-25m-clock-pr.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,89 @@ | ||
| From 9f903328f2169a1d058418a2e49cbe164584b9d9 Mon Sep 17 00:00:00 2001 | ||
| From: Tomer Maimon <[email protected]> | ||
| Date: Mon, 1 Jul 2024 10:10:44 +0300 | ||
| Subject: [PATCH] dt-bindings: clock: npcm845: Add reference 25m clock property | ||
|
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| The NPCM8XX clock driver uses a 25Mhz external clock, therefore adding | ||
| clock property. | ||
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| The new required clock property does not break the NPCM8XX clock ABI | ||
| since the NPCM8XX clock driver hasn't merged yet to the Linux vanilla. | ||
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| This change was pushed upstream and under reviewing: | ||
| https://lore.kernel.org/all/[email protected]/ | ||
|
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||
| Signed-off-by: Tomer Maimon <[email protected]> | ||
| --- | ||
| arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++---- | ||
| arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 7 +++++++ | ||
| 2 files changed, 12 insertions(+), 4 deletions(-) | ||
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| diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| index ecd171b2feba..41d345448430 100644 | ||
| --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| @@ -52,6 +52,7 @@ rstc: reset-controller@f0801000 { | ||
| reg = <0x0 0xf0801000 0x0 0x78>; | ||
| #reset-cells = <2>; | ||
| nuvoton,sysgcr = <&gcr>; | ||
| + clocks = <&refclk>; | ||
| }; | ||
|
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||
| clk: clock-controller@f0801000 { | ||
| @@ -81,7 +82,7 @@ timer0: timer@8000 { | ||
| compatible = "nuvoton,npcm845-timer"; | ||
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg = <0x8000 0x1C>; | ||
| - clocks = <&clk NPCM8XX_CLK_REFCLK>; | ||
| + clocks = <&refclk>; | ||
| clock-names = "refclk"; | ||
| }; | ||
|
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||
| @@ -153,7 +154,7 @@ watchdog0: watchdog@801c { | ||
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg = <0x801c 0x4>; | ||
| status = "disabled"; | ||
| - clocks = <&clk NPCM8XX_CLK_REFCLK>; | ||
| + clocks = <&refclk>; | ||
| syscon = <&gcr>; | ||
| }; | ||
|
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||
| @@ -162,7 +163,7 @@ watchdog1: watchdog@901c { | ||
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg = <0x901c 0x4>; | ||
| status = "disabled"; | ||
| - clocks = <&clk NPCM8XX_CLK_REFCLK>; | ||
| + clocks = <&refclk>; | ||
| syscon = <&gcr>; | ||
| }; | ||
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||
| @@ -171,7 +172,7 @@ watchdog2: watchdog@a01c { | ||
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg = <0xa01c 0x4>; | ||
| status = "disabled"; | ||
| - clocks = <&clk NPCM8XX_CLK_REFCLK>; | ||
| + clocks = <&refclk>; | ||
| syscon = <&gcr>; | ||
| }; | ||
| }; | ||
| diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | ||
| index a5ab2bc0f835..83c2f4e138e5 100644 | ||
| --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | ||
| +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | ||
| @@ -19,6 +19,13 @@ chosen { | ||
| memory { | ||
| reg = <0x0 0x0 0x0 0x40000000>; | ||
| }; | ||
| + | ||
| + refclk: refclk-25mhz { | ||
| + compatible = "fixed-clock"; | ||
| + clock-output-names = "ref"; | ||
| + clock-frequency = <25000000>; | ||
| + #clock-cells = <0>; | ||
| + }; | ||
| }; | ||
|
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||
| &serial0 { | ||
| -- | ||
| 2.34.1 | ||
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|
136 changes: 136 additions & 0 deletions
136
...pes-kernel/linux/linux-nuvoton/1001-arm64-dts-modify-clock-property-in-modules-node.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,136 @@ | ||
| From 7ada4b7e39819f2cc765b27f3fc1ad38ece3278f Mon Sep 17 00:00:00 2001 | ||
| From: Tomer Maimon <[email protected]> | ||
| Date: Mon, 1 Jul 2024 10:10:46 +0300 | ||
| Subject: [PATCH] arm64: dts: modify clock property in modules node | ||
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| Modify clock property handler in UART, CPU, PECI modules to reset | ||
| controller. | ||
|
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||
| This change was pushed upstream and under reviewing: | ||
| https://lore.kernel.org/all/[email protected]/ | ||
|
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||
| Signed-off-by: Tomer Maimon <[email protected]> | ||
| --- | ||
| .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++++-------- | ||
| arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 8 ++++---- | ||
| 2 files changed, 12 insertions(+), 12 deletions(-) | ||
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| diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| index 41d345448430..92e3b0fe746f 100644 | ||
| --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| @@ -73,7 +73,7 @@ peci: peci-controller@100000 { | ||
| compatible = "nuvoton,npcm845-peci"; | ||
| reg = <0x100000 0x1000>; | ||
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | ||
| - clocks = <&clk NPCM8XX_CLK_APB3>; | ||
| + clocks = <&rstc NPCM8XX_CLK_APB3>; | ||
| cmd-timeout-ms = <1000>; | ||
| status = "disabled"; | ||
| }; | ||
| @@ -89,7 +89,7 @@ timer0: timer@8000 { | ||
| serial0: serial@0 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x0 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -98,7 +98,7 @@ serial0: serial@0 { | ||
| serial1: serial@1000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x1000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -107,7 +107,7 @@ serial1: serial@1000 { | ||
| serial2: serial@2000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x2000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -116,7 +116,7 @@ serial2: serial@2000 { | ||
| serial3: serial@3000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x3000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -125,7 +125,7 @@ serial3: serial@3000 { | ||
| serial4: serial@4000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x4000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -134,7 +134,7 @@ serial4: serial@4000 { | ||
| serial5: serial@5000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x5000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART>; | ||
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| @@ -143,7 +143,7 @@ serial5: serial@5000 { | ||
| serial6: serial@6000 { | ||
| compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; | ||
| reg = <0x6000 0x1000>; | ||
| - clocks = <&clk NPCM8XX_CLK_UART>; | ||
| + clocks = <&rstc NPCM8XX_CLK_UART2>; | ||
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| status = "disabled"; | ||
| diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | ||
| index 383938dcd3ce..3cbcea65eba2 100644 | ||
| --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | ||
| +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | ||
| @@ -14,7 +14,7 @@ cpus { | ||
| cpu0: cpu@0 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a35"; | ||
| - clocks = <&clk NPCM8XX_CLK_CPU>; | ||
| + clocks = <&rstc NPCM8XX_CLK_CPU>; | ||
| reg = <0x0 0x0>; | ||
| next-level-cache = <&l2>; | ||
| enable-method = "psci"; | ||
| @@ -23,7 +23,7 @@ cpu0: cpu@0 { | ||
| cpu1: cpu@1 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a35"; | ||
| - clocks = <&clk NPCM8XX_CLK_CPU>; | ||
| + clocks = <&rstc NPCM8XX_CLK_CPU>; | ||
| reg = <0x0 0x1>; | ||
| next-level-cache = <&l2>; | ||
| enable-method = "psci"; | ||
| @@ -32,7 +32,7 @@ cpu1: cpu@1 { | ||
| cpu2: cpu@2 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a35"; | ||
| - clocks = <&clk NPCM8XX_CLK_CPU>; | ||
| + clocks = <&rstc NPCM8XX_CLK_CPU>; | ||
| reg = <0x0 0x2>; | ||
| next-level-cache = <&l2>; | ||
| enable-method = "psci"; | ||
| @@ -41,7 +41,7 @@ cpu2: cpu@2 { | ||
| cpu3: cpu@3 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a35"; | ||
| - clocks = <&clk NPCM8XX_CLK_CPU>; | ||
| + clocks = <&rstc NPCM8XX_CLK_CPU>; | ||
| reg = <0x0 0x3>; | ||
| next-level-cache = <&l2>; | ||
| enable-method = "psci"; | ||
| -- | ||
| 2.34.1 | ||
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44 changes: 44 additions & 0 deletions
44
...ernel/linux/linux-nuvoton/1002-arm64-dts-npmc8xx-move-the-clk-handler-node-to-the-r.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| From d197b1fdad05c195a1f40c4575d9b9b802e7ced1 Mon Sep 17 00:00:00 2001 | ||
| From: Tomer Maimon <[email protected]> | ||
| Date: Mon, 1 Jul 2024 10:10:45 +0300 | ||
| Subject: [PATCH] arm64: dts: npmc8xx: move the clk handler node to the reset | ||
| node | ||
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| Add clk handler node to the reset node and removing the clock node | ||
| driver since the reset driver is register the NPCM8xx clock controller | ||
| aux device. | ||
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| We will push this change upstream for reviewing soon. | ||
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| Signed-off-by: Tomer Maimon <[email protected]> | ||
| --- | ||
| arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +------ | ||
| 1 file changed, 1 insertion(+), 6 deletions(-) | ||
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| diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| index 92e3b0fe746f..01daf0615ccc 100644 | ||
| --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | ||
| @@ -47,18 +47,13 @@ ahb { | ||
| interrupt-parent = <&gic>; | ||
| ranges; | ||
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| - rstc: reset-controller@f0801000 { | ||
| + clk: rstc: reset-controller@f0801000 { | ||
| compatible = "nuvoton,npcm845-reset"; | ||
| reg = <0x0 0xf0801000 0x0 0x78>; | ||
| #reset-cells = <2>; | ||
| nuvoton,sysgcr = <&gcr>; | ||
| clocks = <&refclk>; | ||
| - }; | ||
| - | ||
| - clk: clock-controller@f0801000 { | ||
| - compatible = "nuvoton,npcm845-clk"; | ||
| #clock-cells = <1>; | ||
| - reg = <0x0 0xf0801000 0x0 0x1000>; | ||
| }; | ||
|
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| apb { | ||
| -- | ||
| 2.34.1 | ||
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|
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