Correct/improve some field descriptions for ESP32-S3's LCD_CAM peri…

…pheral
esp-rs · Dec 14, 2023 · 45da44e · 45da44e
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Showing 5 changed files with 89 additions and 48 deletions.
diff --git a/esp32s3/src/lcd_cam/cam_ctrl.rs b/esp32s3/src/lcd_cam/cam_ctrl.rs
@@ -14,13 +14,13 @@ pub type CAM_VSYNC_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 pub type CAM_UPDATE_R = crate::BitReader;
 #[doc = "Field `CAM_UPDATE` writer - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."]
 pub type CAM_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAM_BYTE_ORDER` reader - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."]
+#[doc = "Field `CAM_BYTE_ORDER` reader - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."]
 pub type CAM_BYTE_ORDER_R = crate::BitReader;
-#[doc = "Field `CAM_BYTE_ORDER` writer - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."]
+#[doc = "Field `CAM_BYTE_ORDER` writer - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."]
 pub type CAM_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAM_BIT_ORDER` reader - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."]
+#[doc = "Field `CAM_BIT_ORDER` reader - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
 pub type CAM_BIT_ORDER_R = crate::BitReader;
-#[doc = "Field `CAM_BIT_ORDER` writer - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."]
+#[doc = "Field `CAM_BIT_ORDER` writer - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
 pub type CAM_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CAM_LINE_INT_EN` reader - 1: Enable to generate CAM_HS_INT. 0: Disable."]
 pub type CAM_LINE_INT_EN_R = crate::BitReader;
@@ -62,12 +62,12 @@ impl R {
     pub fn cam_update(&self) -> CAM_UPDATE_R {
         CAM_UPDATE_R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."]
+    #[doc = "Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."]
     #[inline(always)]
     pub fn cam_byte_order(&self) -> CAM_BYTE_ORDER_R {
         CAM_BYTE_ORDER_R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."]
+    #[doc = "Bit 6 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
     #[inline(always)]
     pub fn cam_bit_order(&self) -> CAM_BIT_ORDER_R {
         CAM_BIT_ORDER_R::new(((self.bits >> 6) & 1) != 0)
@@ -173,13 +173,13 @@ impl W {
     pub fn cam_update(&mut self) -> CAM_UPDATE_W<CAM_CTRL_SPEC> {
         CAM_UPDATE_W::new(self, 4)
     }
-    #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."]
+    #[doc = "Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."]
     #[inline(always)]
     #[must_use]
     pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W<CAM_CTRL_SPEC> {
         CAM_BYTE_ORDER_W::new(self, 5)
     }
-    #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."]
+    #[doc = "Bit 6 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."]
     #[inline(always)]
     #[must_use]
     pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W<CAM_CTRL_SPEC> {

diff --git a/esp32s3/src/lcd_cam/cam_ctrl1.rs b/esp32s3/src/lcd_cam/cam_ctrl1.rs
@@ -2,13 +2,13 @@
 pub type R = crate::R<CAM_CTRL1_SPEC>;
 #[doc = "Register `CAM_CTRL1` writer"]
 pub type W = crate::W<CAM_CTRL1_SPEC>;
-#[doc = "Field `CAM_REC_DATA_BYTELEN` reader - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."]
+#[doc = "Field `CAM_REC_DATA_BYTELEN` reader - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
 pub type CAM_REC_DATA_BYTELEN_R = crate::FieldReader<u16>;
-#[doc = "Field `CAM_REC_DATA_BYTELEN` writer - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."]
+#[doc = "Field `CAM_REC_DATA_BYTELEN` writer - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
 pub type CAM_REC_DATA_BYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
-#[doc = "Field `CAM_LINE_INT_NUM` reader - The line number minus 1 to generate cam_hs_int."]
+#[doc = "Field `CAM_LINE_INT_NUM` reader - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."]
 pub type CAM_LINE_INT_NUM_R = crate::FieldReader;
-#[doc = "Field `CAM_LINE_INT_NUM` writer - The line number minus 1 to generate cam_hs_int."]
+#[doc = "Field `CAM_LINE_INT_NUM` writer - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."]
 pub type CAM_LINE_INT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
 #[doc = "Field `CAM_CLK_INV` reader - 1: Invert the input signal CAM_PCLK. 0: Not invert."]
 pub type CAM_CLK_INV_R = crate::BitReader;
@@ -18,9 +18,9 @@ pub type CAM_CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type CAM_VSYNC_FILTER_EN_R = crate::BitReader;
 #[doc = "Field `CAM_VSYNC_FILTER_EN` writer - 1: Enable CAM_VSYNC filter function. 0: bypass."]
 pub type CAM_VSYNC_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAM_2BYTE_EN` reader - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."]
+#[doc = "Field `CAM_2BYTE_EN` reader - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."]
 pub type CAM_2BYTE_EN_R = crate::BitReader;
-#[doc = "Field `CAM_2BYTE_EN` writer - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."]
+#[doc = "Field `CAM_2BYTE_EN` writer - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."]
 pub type CAM_2BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CAM_DE_INV` reader - CAM_DE invert enable signal, valid in high level."]
 pub type CAM_DE_INV_R = crate::BitReader;
@@ -44,15 +44,15 @@ pub type CAM_START_R = crate::BitReader;
 pub type CAM_START_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CAM_RESET` writer - Camera module reset signal."]
 pub type CAM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `CAM_AFIFO_RESET` writer - Camera AFIFO reset signal."]
+#[doc = "Field `CAM_AFIFO_RESET` writer - Camera Async Rx FIFO reset signal."]
 pub type CAM_AFIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
-    #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."]
+    #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
     #[inline(always)]
     pub fn cam_rec_data_bytelen(&self) -> CAM_REC_DATA_BYTELEN_R {
         CAM_REC_DATA_BYTELEN_R::new((self.bits & 0xffff) as u16)
     }
-    #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."]
+    #[doc = "Bits 16:21 - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."]
     #[inline(always)]
     pub fn cam_line_int_num(&self) -> CAM_LINE_INT_NUM_R {
         CAM_LINE_INT_NUM_R::new(((self.bits >> 16) & 0x3f) as u8)
@@ -67,7 +67,7 @@ impl R {
     pub fn cam_vsync_filter_en(&self) -> CAM_VSYNC_FILTER_EN_R {
         CAM_VSYNC_FILTER_EN_R::new(((self.bits >> 23) & 1) != 0)
     }
-    #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."]
+    #[doc = "Bit 24 - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."]
     #[inline(always)]
     pub fn cam_2byte_en(&self) -> CAM_2BYTE_EN_R {
         CAM_2BYTE_EN_R::new(((self.bits >> 24) & 1) != 0)
@@ -143,13 +143,13 @@ impl core::fmt::Debug for crate::generic::Reg<CAM_CTRL1_SPEC> {
     }
 }
 impl W {
-    #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."]
+    #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
     #[inline(always)]
     #[must_use]
     pub fn cam_rec_data_bytelen(&mut self) -> CAM_REC_DATA_BYTELEN_W<CAM_CTRL1_SPEC> {
         CAM_REC_DATA_BYTELEN_W::new(self, 0)
     }
-    #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."]
+    #[doc = "Bits 16:21 - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."]
     #[inline(always)]
     #[must_use]
     pub fn cam_line_int_num(&mut self) -> CAM_LINE_INT_NUM_W<CAM_CTRL1_SPEC> {
@@ -167,7 +167,7 @@ impl W {
     pub fn cam_vsync_filter_en(&mut self) -> CAM_VSYNC_FILTER_EN_W<CAM_CTRL1_SPEC> {
         CAM_VSYNC_FILTER_EN_W::new(self, 23)
     }
-    #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."]
+    #[doc = "Bit 24 - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."]
     #[inline(always)]
     #[must_use]
     pub fn cam_2byte_en(&mut self) -> CAM_2BYTE_EN_W<CAM_CTRL1_SPEC> {
@@ -209,7 +209,7 @@ impl W {
     pub fn cam_reset(&mut self) -> CAM_RESET_W<CAM_CTRL1_SPEC> {
         CAM_RESET_W::new(self, 30)
     }
-    #[doc = "Bit 31 - Camera AFIFO reset signal."]
+    #[doc = "Bit 31 - Camera Async Rx FIFO reset signal."]
     #[inline(always)]
     #[must_use]
     pub fn cam_afifo_reset(&mut self) -> CAM_AFIFO_RESET_W<CAM_CTRL1_SPEC> {

diff --git a/esp32s3/src/lcd_cam/lcd_clock.rs b/esp32s3/src/lcd_cam/lcd_clock.rs
@@ -34,9 +34,9 @@ pub type LCD_CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
 pub type LCD_CLK_SEL_R = crate::FieldReader;
 #[doc = "Field `LCD_CLK_SEL` writer - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."]
 pub type LCD_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
-#[doc = "Field `CLK_EN` reader - Set this bit to enable clk gate"]
+#[doc = "Field `CLK_EN` reader - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
 pub type CLK_EN_R = crate::BitReader;
-#[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"]
+#[doc = "Field `CLK_EN` writer - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
 pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl R {
     #[doc = "Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."]
@@ -79,7 +79,7 @@ impl R {
     pub fn lcd_clk_sel(&self) -> LCD_CLK_SEL_R {
         LCD_CLK_SEL_R::new(((self.bits >> 29) & 3) as u8)
     }
-    #[doc = "Bit 31 - Set this bit to enable clk gate"]
+    #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
     #[inline(always)]
     pub fn clk_en(&self) -> CLK_EN_R {
         CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
@@ -180,7 +180,7 @@ impl W {
     pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W<LCD_CLOCK_SPEC> {
         LCD_CLK_SEL_W::new(self, 29)
     }
-    #[doc = "Bit 31 - Set this bit to enable clk gate"]
+    #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
     #[inline(always)]
     #[must_use]
     pub fn clk_en(&mut self) -> CLK_EN_W<LCD_CLOCK_SPEC> {