Add FROM_CPU_INTRx interrupts for ESP32-P4

esp-rs · Oct 8, 2024 · 37e675f · 37e675f
1 parent c717453
commit 37e675f
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Showing 4 changed files with 54 additions and 13 deletions.
diff --git a/esp32p4/device.x b/esp32p4/device.x
@@ -65,6 +65,10 @@ PROVIDE(GPIO_INT1 = DefaultHandler);
 PROVIDE(GPIO_INT2 = DefaultHandler);
 PROVIDE(GPIO_INT3 = DefaultHandler);
 PROVIDE(GPIO_PAD_COMP = DefaultHandler);
+PROVIDE(FROM_CPU_INTR0 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR1 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR2 = DefaultHandler);
+PROVIDE(FROM_CPU_INTR3 = DefaultHandler);
 PROVIDE(CACHE = DefaultHandler);
 PROVIDE(CSI_BRIDGE = DefaultHandler);
 PROVIDE(DSI_BRIDGE = DefaultHandler);

diff --git a/esp32p4/src/interrupt.rs b/esp32p4/src/interrupt.rs
@@ -137,6 +137,14 @@ pub enum Interrupt {
     GPIO_INT3 = 77,
     #[doc = "78 - GPIO_PAD_COMP"]
     GPIO_PAD_COMP = 78,
+    #[doc = "79 - FROM_CPU_INTR0"]
+    FROM_CPU_INTR0 = 79,
+    #[doc = "80 - FROM_CPU_INTR1"]
+    FROM_CPU_INTR1 = 80,
+    #[doc = "81 - FROM_CPU_INTR2"]
+    FROM_CPU_INTR2 = 81,
+    #[doc = "82 - FROM_CPU_INTR3"]
+    FROM_CPU_INTR3 = 82,
     #[doc = "83 - CACHE"]
     CACHE = 83,
     #[doc = "85 - CSI_BRIDGE"]
@@ -269,6 +277,10 @@ impl Interrupt {
             76 => Ok(Interrupt::GPIO_INT2),
             77 => Ok(Interrupt::GPIO_INT3),
             78 => Ok(Interrupt::GPIO_PAD_COMP),
+            79 => Ok(Interrupt::FROM_CPU_INTR0),
+            80 => Ok(Interrupt::FROM_CPU_INTR1),
+            81 => Ok(Interrupt::FROM_CPU_INTR2),
+            82 => Ok(Interrupt::FROM_CPU_INTR3),
             83 => Ok(Interrupt::CACHE),
             85 => Ok(Interrupt::CSI_BRIDGE),
             86 => Ok(Interrupt::DSI_BRIDGE),

diff --git a/esp32p4/src/lib.rs b/esp32p4/src/lib.rs
@@ -80,6 +80,10 @@ extern "C" {
     fn GPIO_INT2();
     fn GPIO_INT3();
     fn GPIO_PAD_COMP();
+    fn FROM_CPU_INTR0();
+    fn FROM_CPU_INTR1();
+    fn FROM_CPU_INTR2();
+    fn FROM_CPU_INTR3();
     fn CACHE();
     fn CSI_BRIDGE();
     fn DSI_BRIDGE();
@@ -243,10 +247,18 @@ pub static __EXTERNAL_INTERRUPTS: [Vector; 128] = [
     Vector {
         _handler: GPIO_PAD_COMP,
     },
-    Vector { _reserved: 0 },
-    Vector { _reserved: 0 },
-    Vector { _reserved: 0 },
-    Vector { _reserved: 0 },
+    Vector {
+        _handler: FROM_CPU_INTR0,
+    },
+    Vector {
+        _handler: FROM_CPU_INTR1,
+    },
+    Vector {
+        _handler: FROM_CPU_INTR2,
+    },
+    Vector {
+        _handler: FROM_CPU_INTR3,
+    },
     Vector { _handler: CACHE },
     Vector { _reserved: 0 },
     Vector {

diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml
@@ -157,7 +157,8 @@ PCNT:
         CH?_HCTRL_MODE:
           _name: CtrlMode
           Keep: [0, No modification]
-          Reverse: [1, Invert behavior (increase -> decrease, decrease -> increase)]
+          Reverse:
+            [1, Invert behavior (increase -> decrease, decrease -> increase)]
           Disable: [-1, Inhibit counter modification]
       U?_CONF1:
         name: CONF1
@@ -223,8 +224,8 @@ SPI[23]:
   "*":
     _strip: SPI_
   _include:
-   - ../../../common_patches/spi_dma_int_strip.yaml
-   - ../../../common_patches/spi_w.yaml
+    - ../../../common_patches/spi_dma_int_strip.yaml
+    - ../../../common_patches/spi_w.yaml
 
 SOC_ETM:
   _include: ../../../common_patches/etm_collect.yaml
@@ -313,7 +314,7 @@ MCPWM0:
   _include: ../../../common_patches/int_strip.yaml
 
 SYSTIMER:
-  _include: 
+  _include:
     - ../../../common_patches/int_strip.yaml
     - ../../../common_patches/systimer.yaml
     - ../../../common_patches/systimer_real_target.yaml
@@ -405,7 +406,7 @@ AHB_DMA:
     OUT_INT_ST_CH%s: {}
     OUT_INT_ENA_CH%s: {}
     OUT_INT_CLR_CH%s: {}
-  
+
     OUT_CRC_INIT_DATA_CH%s: {}
     TX_CRC_WIDTH_CH%s: {}
     OUT_CRC_CLEAR_CH%s: {}
@@ -484,7 +485,7 @@ AHB_DMA:
         _modify:
           "*":
             modifiedWriteValues: oneToClear
-    
+
     OUT_CRC_CH%s:
       OUT_CRC_INIT_DATA_CH?:
         name: OUT_CRC_INIT_DATA
@@ -707,7 +708,7 @@ AXI_DMA:
     TX_CRC_EN_ADDR_CH%s: {}
     TX_CRC_DATA_EN_WR_DATA_CH%s: {}
     TX_CRC_DATA_EN_ADDR_CH%s: {}
-  
+
   _cluster:
     IN_CH%s:
       _cluster:
@@ -720,7 +721,7 @@ AXI_DMA:
             name: ENA
           IN_INT_CLR:
             name: CLR
-        
+
         CRC:
           IN_CRC_INIT_DATA: {}
           RX_CRC_WIDTH: {}
@@ -821,7 +822,7 @@ AXI_DMA:
             name: ENA
           OUT_INT_CLR:
             name: CLR
-        
+
         CRC:
           OUT_CRC_INIT_DATA: {}
           TX_CRC_WIDTH: {}
@@ -1336,3 +1337,15 @@ LCD_CAM:
     _array:
       DOUT*_MODE:
         description: The output data bit %s is delayed by module clock LCD_CLK
+
+HP_SYS:
+  _add:
+    _interrupts:
+      FROM_CPU_INTR0:
+        value: 79
+      FROM_CPU_INTR1:
+        value: 80
+      FROM_CPU_INTR2:
+        value: 81
+      FROM_CPU_INTR3:
+        value: 82