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Draft: Add m-mode CLIC interrupt testcases
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,218 @@ | ||
| ==== clicnomint-01.S | ||
| .Description: expect interrupts will not trigger in m-mode unless mstatus.mie is set | ||
| - enable clicintie (default) | ||
| - generate interrupt1 | ||
| - nop | ||
| - jump to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_MSTATUS_MIE = 0 | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_WFI = nop | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| mstatus.mie | verify no interrupt occurs in m-mode if mstatus.mie is 0 | ||
| ---- | ||
| ==== clicnomint-02.S | ||
| .Description: expect interrupts will not trigger in m-mode unless clicintie.x is set | ||
| - disable clicintie | ||
| - generate interrupt1 | ||
| - enable mstatus.mie | ||
| - nop | ||
| - jump to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_INT1_CLICINTIE = 0 | ||
| RVMODEL_INT2_CLICINTIE = 0 | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_WFI = nop | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| clicintie[msw] | verify no msw interrupt occurs if clicintie[msw] is 0 | ||
| clicintie[mtimer] | verify no mtimer interrupt occurs if clicintie[mtimer] is 0 | ||
| ---- | ||
| ==== clicnomint-03.S | ||
| .Description: expect interrupts will not trigger in m-mode unless clicintctrl.x > mintthresh | ||
| - enable clicintie (default) | ||
| - generate interrupt1 | ||
| - enable mstatus.mie | ||
| - nop | ||
| - jump to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_MINTTHRESH = RVMODEL_MINTTHRESH_MAX | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_WFI = nop | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| mintthresh | verify no msw interrupt occurs if mintthresh is max | ||
| ---- | ||
| ==== clicwfi-01.S | ||
| .Description: expect wfi to behave like a nop when a single interrupt is pending when mstatus.mie is disabled | ||
| - enable clicintie (default) | ||
| - generate interrupt1 | ||
| - wfi | ||
| - wakeup | ||
| - jump to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_MSTATUS_MIE = 0 | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| mstatus.mie | verify no interrupt occurs in m-mode if mstatus.mie is 0 | ||
| wfi | verify wakeup/nop occurs with mstatus.mie = 0 | ||
| wfi | verify wakeup/nop occurs with pending interrupt | ||
| ---- | ||
| ==== clicdirect-01.S | ||
| .Description: trigger, clear, no retrigger of same interrupt. Will hang if no interrupt occurs | ||
| - enable clicintie (default) | ||
| - generate interrupt1 | ||
| - enable mstatus.mie | ||
| - trigger m-mode handler | ||
| - clear 1st interrupt | ||
| - generate interrupt1 again (ignored) | ||
| - set mepc to finish | ||
| - mret to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT | ||
| RVMODEL_MINTTHRESH = RVMODEL_MINTTHRESH_MIN | ||
| RVMODEL_WFI = jump_to_self | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| mtvec.mode | verify direct mode is used to handle interrupt | ||
| no msip retrigger | verify after mstatus.mie is enabled in interrupt handler, msip will not retrigger because msip intlevel is not > mintstatus | ||
| msip trigger | verify RVMODEL_SET_MSW_INT trigger | ||
| msip clear | verify RVMODEL_CLEAR_MSW_INT clear | ||
| mcause | verify machine software interrupt signature | ||
| mstatus | verify mstatus.mie/mpie/mpp signature in interrupt handler and after mret | ||
| mtvec | verify interrupt uses mtvec to calculate pc of interrupt handler (direct) | ||
| mepc | verify mepc location is jump_to_self location | ||
| ---- | ||
| ==== cliclevel-01.S | ||
| .Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, min level int followed by max level int | ||
| - enable clicintie (default) | ||
| - generate interrupt 1 | ||
| - enable mstatus.mie | ||
| - trigger m-mode handler | ||
| - generate interrupt 2 (both interrupts now pending) | ||
| - if clicintctrl represents levels, mnxti csrrsi updates mcause.id for 2nd interrupt | ||
| - if clicintctrl represents priority, no 2nd interrupt occurs. | ||
| - set mepc to finish | ||
| - clear mstatus.mpie | ||
| - mret to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = <EMPTY> | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_INT1_CLICINTCTL = RVMODEL_CLICINTCTL_MIN | ||
| RVMODEL_INT2_CLICINTCTL = RVMODEL_CLICINTCTL_MAX | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| Interrupt ordering - both interrupts asserted in first interrupt handler | ||
| ---- | ||
|
|
||
| ==== cliclevel-02.S | ||
| .Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, min level int followed by max level int | ||
| - enable clicintie (default) | ||
| - generate interrupt 1 | ||
| - enable mstatus.mie | ||
| - trigger m-mode handler | ||
| - generate interrupt 2 (both interrupts now pending) | ||
| - if clicintctrl represents levels, trigger 2nd m-mode handler | ||
| - if clicintctrl represents priority, no 2nd interrupt occurs. | ||
| - set mepc to finish | ||
| - clear mstatus.mpie | ||
| - mret to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = <EMPTY> | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_INT1_CLICINTCTL = RVMODEL_CLICINTCTL_MIN | ||
| RVMODEL_INT2_CLICINTCTL = RVMODEL_CLICINTCTL_MAX | ||
| RVMODEL_MNXTI_SIMMED = 0 | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| Interrupt ordering - both interrupts asserted in first interrupt handler | ||
| ---- | ||
|
|
||
| ==== cliclevel-03.S | ||
| .Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, max level int followed by min level int | ||
| - enable clicintie (default) | ||
| - generate interrupt 1 | ||
| - enable mstatus.mie | ||
| - trigger m-mode handler | ||
| - generate interrupt 2 (both interrupts now pending) | ||
| - if clicintctrl represents levels, 2nd interrupt is lower than current interupt level, no 2nd interrupt occurs. | ||
| - if clicintctrl represents priority, 2nd interrupt is same level, no 2nd interrupt occurs. | ||
| - set mepc to finish | ||
| - clear mstatus.mpie | ||
| - mret to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = <EMPTY> | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_INT1_CLICINTCTL = RVMODEL_CLICINTCTL_MAX | ||
| RVMODEL_INT2_CLICINTCTL = RVMODEL_CLICINTCTL_MIN | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| Interrupt ordering - both interrupts asserted in first interrupt handler | ||
| ---- | ||
|
|
||
| ==== cliclevel-04.S | ||
| .Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, min level int followed by max level int with max mintthresh setting. | ||
| - enable clicintie (default) | ||
| - generate interrupt 1 | ||
| - enable mstatus.mie | ||
| - trigger m-mode handler | ||
| - generate interrupt 2 (both interrupts now pending) | ||
| - if clicintctrl represents levels, 2nd interrupt is higher than current interupt level but equal to mintthresh, no 2nd interrupt occurs. | ||
| - if clicintctrl represents priority, 2nd interrupt is same level, no 2nd interrupt occurs. | ||
| - set mepc to finish | ||
| - clear mstatus.mpie | ||
| - mret to finish | ||
| [%autofit] | ||
| ---- | ||
| RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT | ||
| RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT | ||
| RVMODEL_CLEAR_INT1 = <EMPTY> | ||
| RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT | ||
| RVMODEL_INT1_CLICINTCTL = RVMODEL_CLICINTCTL_MIN | ||
| RVMODEL_INT2_CLICINTCTL = RVMODEL_CLICINTCTL_MAX | ||
| RVMODEL_MINTTHRESH_HNDLR1 = RVMODEL_MINTTHRESH_MAX | ||
| ---- | ||
| Coverage | ||
| ---- | ||
| Interrupt ordering - both interrupts asserted in first interrupt handler | ||
| ---- |