Conflicting requirement in Caliptra fuse register reset and lock definition

[myviewfinder]

Conflicting requirements within the first paragraph of Fuse requirements pasted below:

"Fuse registers are programmable whenever IP goes through reset (after cptra_rst_b asserts and de-asserts) and before the fuse registers are locked from writes. If the lock was set, the writes are dropped. The lock is sticky across a warm reset."

Specifically, the lock that is sticky across warm reset would prevent SoC from writing to the Caliptra fuse registers after cptra_rst_b assertion & de-assertion due to Warm Reset (see ref.). Does the Caliptra Main Specification intend to say "cptra_pwrgood de-asserts and asserts" instead of cptra_rst_b above?

Refer to the CPTRA_FUSE_WR_DONE register's reset signal definition of cptra_pwrgood, which matches the sticky requirement above. In addition, all Caliptra fuse_* registers have reset signal definition of cptr_pwrgood.