Update Hardware Specifications to Indicate Two SHA512 core instances

[dbids]

I've been working with integrating Caliptra for a number of months now and only today realized that there are two instances of the SHA512 core in the logic. It would be great if the hardware documentation could be updated to state this clearly, as it required delving into the RTL for me to confirm my suspicions (something an integrator of Caliptra ideally should not have to do). In addition, it is imperative that those integrating Caliptra know how many SHA instances exist within it to meet FIPS 140-3 requirements.

Here are my suggested changes:

• CaliptraHardwareSpecification : SHA accelerator HW API
  • Add a mention of a SHA hardware instance that is leveraged by the API, noting that it is a separate instance that uses the same core as the SHA512 accelerator in the cryptographic subsystem w/o some of the surrounding logic.
• CaliptraIntegrationSpecification : Figure 1
  • Add a SHA accelerator block within the SoC interface block on the diagram, as fits the logical hierarchy.
• CaliptraMainSpecification : Figure 8
  • Update Figure 8 to have a SHA512 accelerator within the SoC interface. Again, it is important that integrators know the number of SHA blocks within Caliptra from the onset, so keeping the initial spec that they would read up to date is necessary.

[bharatpillilli]

This is not necessary because Caliptra 2.0 passive/subsystem modes will not have SHA Accelerator API anymore