This Git repository contains the source code and design files for a 16-bit CPU implemented in VHDL. The project aims to create a fully-functional CPU that can execute basic instructions of SISA instruction set and support memory access, with a focus on simplicity and ease of understanding.
The repository contains several directories, including introductory exercices, source code for the CPU itself, as well as testbenches, simulation files, and documentation. Users can clone the repository to their local machines and modify the design as needed.
Overall, this Git repository provides a valuable resource for those interested in CPU design and VHDL programming, offering a clear and concise example of a functional 16-bit CPU implementation.