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port for WeAct Studio H723VG-LCD dev board #9550

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@bshewan bshewan commented Aug 22, 2024

Port for this board: https://github.com/WeActStudio/WeActStudio.MiniSTM32H723

  • includes:
    • support for the QSPI Flash as the main CIRCUITPY drive
    • support for OLED display
    • support for the SD card

@bshewan bshewan force-pushed the weact-h723vg-lcd-port branch 3 times, most recently from 5bef472 to cec4a45 Compare August 23, 2024 13:05
@bshewan bshewan force-pushed the weact-h723vg-lcd-port branch from cec4a45 to 6004174 Compare August 23, 2024 17:50
@tannewt tannewt added stm board New board or update to a single board labels Aug 27, 2024
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Thanks for the changes! I'd love to support the 723. However, I'm concerned that some of these changes will break the existing H7 support.

@@ -80,7 +80,7 @@ SECTIONS
_ld_d1_ram_bss_start = ADDR(.bss);
_ld_d1_ram_bss_size = SIZEOF(.bss);
_ld_heap_start = _ld_d1_ram_bss_start + _ld_d1_ram_bss_size;
_ld_heap_end = ORIGIN(RAM) + LENGTH(RAM);
_ld_heap_end = ORIGIN(RAM) + LENGTH(RAM) - 1;
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What is the last byte used for?

Comment on lines +1 to +2
USB_VID = 0x0483
USB_PID = 0x5740
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This is a generic STM VID/PID. If you don't work for WeAct you can request a USB PID from: https://pid.codes/ If you do work for WeAct, then you should sublicense a unique PID from STM or acquire your own VID from the USB folks.

@@ -37,7 +37,7 @@ extern "C" {
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined(HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
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Why change the default? Shouldn't the board define this?

@@ -44,12 +48,12 @@ void stm32_peripherals_clocks_init(void) {
RCC_OscInitStruct.HSEState = BOARD_HSE_SOURCE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000;
RCC_OscInitStruct.PLL.PLLM = 2;
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Does this break other H7 boards?

@@ -185,7 +185,7 @@ void port_internal_flash_flush(void) {
uint32_t sector_size;
uint32_t sector_start_addr = 0xffffffff;
#if defined(STM32H7)
EraseInitStruct.Banks = get_bank(_cache_flash_addr);
// EraseInitStruct.Banks = get_bank(_cache_flash_addr);
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Why not set this?

Comment on lines -119 to +130
__HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
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Do some H7 have two USB peripherals? The board should probably configure which to use.

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