The VSD Squadron board's chip was designed using the flow discussed in this workshop.This chip is a 48 pin QFN package.Inverter is used as the macro in this workshop.
https://vsdsquadron.vlsisystemdesign.com/digital-vlsi-soc-design-and-planning/
This a typical Board that contains an SOC with peripherals.Our focus is on the chip/processor.
This is an example of QFN-48 package.The chip is connected with the package using wirebonds.
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Package : A package is the external casing that surrounds and protects the integrated circuit (IC) die. This casing provides mechanical support, electrical connections, and protection against environmental factors such as moisture, dust, and physical damage. The package also facilitates the connection of the chip to external components or circuitry, typically through pins or solder balls.Packages come in various forms and sizes, ranging from small, surface-mount packages like quad flat no-leads (QFN) and ball grid arrays (BGAs) to larger, through-hole packages like dual in-line packages (DIPs) and small outline integrated circuits (SOICs). The choice of package depends on factors such as the intended application, space constraints, thermal considerations, and manufacturing requirements.
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QFN-48 : A QFN-48 package is a type of integrated circuit packaging commonly used in modern semiconductor devices. This package features a square shape measuring 7mm by 7mm, with leads on all four sides, providing a compact and efficient solution for mounting semiconductor chips onto printed circuit boards (PCBs). The absence of traditional wire leads reduces the overall size of the package and enhances thermal performance, making it suitable for applications where space and heat dissipation are critical concerns, such as mobile devices, consumer electronics, and automotive systems.
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Wirebonds : Wire bonding is a method used in semiconductor manufacturing to create electrical connections between the integrated circuit (IC) die and the external leads of the chip package. Thin wires made of gold or aluminum are attached to bond pads on the die and the package substrate using specialized equipment.
Components of a chip:
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Pads: These are areas on the surface of the chip used for making electrical connections. Pads typically connect the chip to external components or the package.
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Core: The core of a chip refers to its central processing unit (CPU) or the primary computational component where most of the processing tasks occur.
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Die: The die is the small, square or rectangular piece of semiconductor material that contains the integrated circuitry of the chip. It's typically made from silicon and contains the transistors, resistors, and other components that make up the chip's functionality.
This is an example of a typical RISC-V chip.
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Foundry : A foundry is a specialized facility that manufactures integrated circuits for semiconductor design companies. It provides the equipment and expertise for high-volume production of chips, allowing companies to prototype and produce electronics without their own manufacturing facilities.
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Intellectual Property : It refers to inventions, designs, and processes, that are legally protected under patents, copyrights, or trade secrets.
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Foundry IPs:In chip design, IP can include pre-designed circuit blocks, algorithms, or software modules that are licensed or owned by companies for integration into their own designs, saving time and resources.Foundry IPs can include standard cell libraries, memory compilers, I/O libraries, analog and mixed-signal IPs, and various other building blocks required for chip design.
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Macros : They are pre-designed and pre-verified blocks of digital circuitry that perform specific functions. These macros are often complex and can include components such as arithmetic units, memory controllers, or communication interfaces. Designers use macros to expedite the development process by integrating proven, reusable blocks into their designs, rather than designing them from scratch. This approach saves time and effort and helps ensure reliability and consistency in chip design.
If a user wants to run a certain program in a chip (here a swap c code) , the abstract flow goes like compiling the program,what happens behind is converting the code(Specs) to a assembly langugae program/instructions based on its architecture(here RISC-V) which is then converted to a machine language program(binary).Concurrently,a RTL corresponding to the specs(here picorv32) is generated which through RTL2GDSII flow can be physically realized on a chip.
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RISC-V : RISC-V is an open-source instruction set architecture (ISA) that defines the instructions and functionalities of a computer's central processing unit (CPU).
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PicoRV32 CPU core : It is a lightweight and compact implementation of the RISC-V ISA.It is known for its small size, low power consumption, and ease of integration into FPGA (Field-Programmable Gate Array) designs. Despite its simplicity, PicoRV32 still provides essential features such as pipelining, branch prediction, and support for both 32-bit and 64-bit RISC-V instructions.
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Qflow layout : Qflow is an open-source digital synthesis and layout tool flow used in the design of integrated circuits (ICs). It provides a suite of tools for performing various steps in the chip design process, including synthesis, place and route, and layout generation.
Similar to the flow discussed in the previous section,we see the flow starting from a software application.
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Instruction Set Architecture : ISA defines the set of instructions and how they are encoded for a specific CPU architecture. It dictates how software communicates with the hardware, specifying operations like arithmetic, data movement, and control flow. ISAs can vary widely, influencing factors such as performance, power efficiency, and software compatibility.
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RTL : It is a hardware description language abstraction level used in digital circuit design. It describes the behavior of a digital system by detailing the flow of data between registers and logic elements. RTL designs are closer to the hardware implementation, making them suitable for synthesis and subsequent physical design stages.
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synthesized netlist : It is a digital blueprint of a circuit created after synthesis. It lists the electronic components and connections, representing the logical structure of the circuit without detailing its physical layout. This netlist serves as an intermediate step for further optimization and analysis in the chip design process before actual implementation.
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Physical Design : Physical design involves the transformation of a logical design (such as RTL) into a physical layout that can be manufactured as a semiconductor chip.It encompasses tasks like floorplanning, placement, routing, and verification
Asic Enablers:
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EDA tools : Electronic Design Automation tools are software applications used in electronic system and integrated circuit design. They automate tasks like schematic capture, simulation, synthesis, place and route, timing analysis, physical verification, and power analysis. These tools are crucial for creating complex electronic systems efficiently and accurately, reducing development time and cost.
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PDK : Process Design Kit is a collection of files and documents provided by semiconductor foundries to support the design of ICs using their manufacturing processes. PDKs contain information about the foundry's fabrication processes, including design rules, device models, parameterized cells (PCells), technology files, and simulation models. Designers use PDKs with EDA tools to create custom IC layouts and verify their designs before manufacturing.
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Open Source PDK : The Open Source PDK from Google and SkyWater Technology Foundry offers a freely available Process Design Kit (PDK) based on the 130nm technology node. Github
Is 130nm old and not in use?
6%-4.5B revenue.Despite its age, 130nm technology still finds use in various specialized applications where cost, power efficiency, and reliability are more critical than cutting-edge performance or density.Intel
Is 130nm fast?
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It is capable of supporting clock speeds sufficient for various applications, especially when coupled with optimized designs and modern design methodologies.
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Intel P4EE(Q4'o4) : The Intel Pentium 4 Extreme Edition (P4EE) processor, released in Q4 of 2004, operated at a clock speed of 3.46 GHz. This high clock speed was achieved through aggressive transistor scaling and optimization techniques available at the time
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sky130_OSU (single cycle RV32i CPU) : Designed using the open-source PDK for the 130nm process node, it can achieve a clock speed of more than 1 GHz.
Several steps-Methodology-RT2GDS/Automated Pnr/Physical Implementation
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Synthesis : This stage involves translating a high-level hardware description into a netlist of logic gates and flip-flops. It's the process of converting RTL design into a gate-level representation.
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Standard cells : Standard cells are basic components in digital integrated circuit design, comprising pre-designed logic gates and flip-flops.Provided by semiconductor foundries as part of a PDK, standard cells offer benefits such as faster design turnaround time and improved manufacturability.
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Floor/Power Planning : In this stage, designers decide how to partition the chip's layout space and allocate resources such as power supplies and signal routing channels. It involves making decisions about where to place major components and how to manage power distribution.
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Chip Floorplan involves the initial layout planning of the various components and functional blocks on a semiconductor chip. It determines the placement of major elements such as the CPU core, memory blocks, I/O interfaces, and other components to optimize factors like signal routing, power distribution, and thermal considerations.
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Macro Floorplan is a more detailed level of floorplanning focusing on specific macro-level functional blocks within the chip. These macros could include complex components such as memory arrays, processors, or specialized IP blocks. Macro floorplanning involves determining the physical placement and interconnection of these blocks to meet performance, area, and power targets while adhering to design constraints and specifications.
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Placement : Placement involves determining the physical location of each logic gate, flip-flop, and other components on the chip's layout. It aims to minimize wire length and optimize performance metrics such as timing and power consumption.
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Global placement : Also known as coarse placement or initial placement, is the first stage of the placement process. It involves roughly positioning the cells or modules of the design on the chip's layout while considering factors like timing, power, and area constraints. Global placement aims to achieve a rough approximation of the final placement layout before refining the positions in the detailed placement stage.
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Detailed placement : Also known as fine placement, follows global placement and involves refining the positions of individual cells or modules on the chip's layout. Detailed placement focuses on optimizing factors such as wirelength, timing, and congestion while ensuring that design constraints are met. This stage often employs advanced algorithms and techniques to achieve high-quality placement results, which directly impact the performance and manufacturability of the chip.
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Clock Tree Synthesis : This stage involves designing the clock distribution network on the chip to ensure that clock signals reach all parts of the design with minimal skew and jitter. It includes synthesizing buffers and routing clock signals to different parts of the chip.
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Clock Skew : It refers to variations in the arrival times of clock signals at different parts of a digital circuit. It can cause timing issues and impact the performance of the circuit. Minimizing clock skew is crucial for ensuring reliable operation.
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Routing : Routing is the process of determining the paths for connecting the various components on the chip layout while obeying design rules and constraints. It involves routing wires to connect the outputs of one component to the inputs of another.
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Global routing : Also known as rough routing, is the initial stage of routing where the approximate paths for interconnecting the various components of the design are determined. It involves finding high-level routes between blocks or modules while considering factors such as wirelength, congestion, and timing constraints. Global routing creates a rough layout of the routing tracks and establishes the overall connectivity of the design.
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Detailed routing : Also known as fine routing, follows global routing and involves refining the routing paths to meet design specifications and constraints. In this stage, individual wires or nets are routed within the routing tracks established during global routing.
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Sign-off : Sign-off refers to the final stage of the design process, where the chip design is verified against various criteria such as timing, power, and signal integrity. It involves running extensive simulations and tests to ensure that the design meets all specifications and requirements before sending it for fabrication.
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Design Rule Checking : DRC is a process used in semiconductor design to ensure that the layout of an integrated circuit adheres to the manufacturing rules and constraints specified by the foundry or design team. It involves automatically checking the layout against a set of design rules to identify violations such as minimum feature sizes, spacing requirements, overlap violations, and other geometric violations. DRC is essential for detecting potential manufacturing defects and ensuring the manufacturability and reliability of the chip.
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Layout vs. Schematic : LVS is a verification process used to ensure the accuracy and consistency between the layout of an integrated circuit and its corresponding schematic or netlist representation. LVS compares the geometric layout of the transistors, wires, and other components against the connectivity and electrical properties specified in the schematic. It checks for discrepancies such as missing connections, extra connections, and electrical mismatches. LVS is critical for identifying design errors and ensuring the functional correctness of the chip.
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Static Timing Analysis : STA is a method used to analyze and verify the timing behavior of an integrated circuit design. It evaluates the timing characteristics of the digital circuit to ensure that signals propagate correctly and meet timing requirements such as setup and hold times. STA considers factors such as gate delays, wire delays, clock skew, and signal arrival times to predict the circuit's performance under different operating conditions. STA helps identify timing violations and ensures that the design operates reliably at the desired clock frequency.
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OpenLane is an open-source digital ASIC (Application-Specific Integrated Circuit) design flow framework developed by efabless and Google. It provides a complete RTL-to-GDSII design flow for designing and fabricating integrated circuits using standard cell libraries and open-source tools.It can be used to harden Macros and chips.Two mode of operation-Autonomus,Interactive.It has large number of design examples(43 designs with their best configurations).
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striVe is a family of open everything SoCs: Open PDK, Open EDA and Open RTL.
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clean GDSII means No LVS/DRC/timing violations.
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Yosys : Yosys is an open-source synthesis tool that transforms RTL (Register Transfer Level) code into a gate-level netlist. It performs logic optimization and technology mapping, converting the design into a format suitable for physical implementation.
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abc : ABC is used for logic optimization and technology mapping during synthesis. It converts RTL descriptions into optimized gate-level netlists, enhancing design efficiency and effectiveness.
Static Timing Analysis:
- OpenSTA : OpenSTA is a static timing analysis tool used for analyzing and verifying timing constraints. It evaluates timing paths in the design to ensure that signals meet timing requirements and identifies timing violations.
- Synthesis Exploration: Refers to the process of exploring various synthesis options and parameters to optimize the RTL-to-gate-level conversion. Designers can experiment with different synthesis configurations to achieve better results in terms of area, power, and timing.
- Design Exploration: Involves exploring different design configurations and constraints to achieve desired performance metrics. Designers can iterate through multiple design options, adjusting parameters such as clock frequency, power constraints, and design goals to find the best design solution.
- Regression Testing: Is the practice of running automated tests on a set of design revisions or configurations to ensure that changes do not introduce regressions or unintended side effects. In OpenLANE, regression testing helps validate design changes and optimizations while maintaining design integrity and quality.
DFT:
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Fault : Fault is a tool for performing fault simulation and testing to verify the robustness and reliability of the design. It identifies potential faults and assesses the impact on circuit functionality.
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Design for Test : It encompasses techniques and methodologies in chip design to enhance testing efficiency and effectiveness. It includes methods like scan chains, built-in self-test (BIST), boundary scan (JTAG), memory BIST, and logic BIST, ensuring thorough testing and fault detection in integrated circuits. DFT aims to improve testability, reduce test costs, and expedite time-to-market.
Physical Implementation:
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OpenROAD : OpenROAD is a set of open-source tools for RTL-to-GDSII implementation. It includes tools for floorplanning, placement, and routing, enabling physical design optimization while considering factors like area, timing, and power.
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TritonRoute : TritonRoute is a detailed router included in OpenLANE for performing global and detailed routing. It optimizes the routing paths while adhering to design rules and constraints, ensuring signal integrity and manufacturability.
Dealing with Antenna Rules Violations:
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Antenna rule violations : It can occur during the manufacturing process of integrated circuits when certain regions of the chip become susceptible to charge accumulation or depletion. These violations can lead to reliability issues, such as gate oxide breakdown or circuit malfunction, and need to be addressed during the design phase.
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Bridging : It involves adding metal connections to neutralize the charge buildup or depletion in susceptible regions. By connecting these regions to a power or ground rail, the charge is dissipated, mitigating the risk of reliability issues.
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Inserting Antenna Diodes:Antenna diodes are specialized diodes inserted into vulnerable regions of the chip to provide a low-resistance path for charge dissipation. These diodes divert any accumulated charge to prevent reliability problems.
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Fake Antenna Diodes: It refers to a technique used to address antenna rule violations during physical design optimization. Instead of inserting actual diodes, fake diodes are virtually inserted into the design layout to satisfy the antenna rules without altering the circuit's functionality. This approach allows designers to meet manufacturing requirements without introducing unnecessary components into the design.
LEC:
- Logical Equivalence Checking : LEC is a formal verification technique used to compare two designs or design representations to ensure that they are functionally equivalent. It checks whether the behavior specified in the RTL description matches that of the gate-level netlist after synthesis
Physical Verification DRC&LVS :
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Magic : Magic is a layout tool used for viewing, editing, and verifying physical layout designs. It allows designers to inspect the layout at different levels of abstraction and perform manual optimizations if needed.
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Netgen : Netgen is a tool for performing LVS (Layout vs. Schematic) and DRC (Design Rule Checking) verification. It compares the layout against the schematic and checks for discrepancies and violations to ensure design correctness.
cd Desktop/work/tools/openlane_working_dir/
cd pdks
cd sky130A
cd libs.ref
cd ..
cd libs.techSKY130 PDK libraries:
There are seven standard cell libraries provided directly by the SkyWater Technology foundry available for use on SKY130 designs, which differ in intended applications and come in three separate cell heights.Libraries in the SKY130 PDK are named using the following scheme:<Process name> _ <Library Source Abbreviation> _ <Library Type Abbreviation> [_ <Library Name>] sky130_fd_sc_hd.lib:
The sky130_fd_sc_hd library is designed for high density. This library enables higher routed gated density, lower dynamic power consumption, and comparable timing and leakage power. As a trade-off it has lower drive strength.- Sky130 : It is the name of the process technology.
- fd : It is abbreviation for who created and is responsible for the library, here the SkyWater Foundry.
- sc : It is abbreviation for the type of content found in the library, here the Digital Standard Cells.
- hd : It represents high density.
cd sky130_fd_sc_hd
cd lib
cd ..
cd lef
cd ..
cd techlef
cd Desktop/work/tools/openlane_working_dir/openlane
docker
pwd
ls -ltr
./flow.tcl -interactive
package require openlane 0.9
cd Desktop/work/tools/openlane_working_dir/openlane
cd designs
ls -ltr
cd picorv32a/
ls-ltr
cd src
less config.tcl #exit by pressing q
less sky130A_sky130_fd_sc_hd_config.tcl
ls -ltr
cd runs
cd 14-04-19-44/
cd tmp
less merged.lef
cd results
cd synthesis
cd reports
ls
less config.tcl #go to end by pressing "Ctrl + End" or "Fn + Right Arrow" and exit by pressing q
less cmds.log
prep -design picorv32a
run_synthesisAutonomous mode:
./flow.tcl -design designname
Interactive Mode:
You may run the flow interactively by using the -interactive option:
./flow.tcl -interactive
A tcl shell will be opened where the openlane package is automatically sourced:
% package require openlane
Then, you should be able to run the following main commands:
- Any tcl command.
prep -design <design> -tag <tag> -config <config> -init_design_config -overwritesimilar to the command line arguments, design is required and the rest is optionalrun_synthesisrun_floorplanrun_placementrun_ctsrun_routingwrite_powered_verilogfollowed byset_netlist $::env(routing_logs)/$::env(DESIGN_NAME).powered.vrun_magicrun_magic_spice_exportrun_magic_drcrun_lvsrun_antenna_check
The above commands can also be written in a file and passed to flow.tcl:
./flow.tcl -interactive -file <file>
cd results
cd synthesis
cd ..
cd ..
cd reports
cd synthesis
less picorv32a.synthesis.v
less 1-yosys_4.stat.rpt
less 2-opensta.rpt
less 2-opensta.timing.rptSection 2 - Good floorplan vs bad floorplan and introduction to library cells (13/03/2024 - 14/03/2024)
Defining the width and height of oore and die is the first step PD flow
Finding values of H&W:
Basic Netlist (launch flop and capture flop with combinational logic)
Providing proper dimensions to the logic gates
Dimensions of the wire can be neglected for the calculation
Clubing them to a single plate
Place the cells inside core
In case of 100% Utilization,Adding extra cells is not allowed,ideally 50/60% is prefered .
In case of Aspect Ratio = 1,then its a square shaped core,otherwise rectangle.
In a diff dimension,
UF < 1,Some more area is present which can be utilized/Optimisation required.
cd configuration
Before running floorplan command enable certain switches
less README.md
less floorplan.tcl(FP_IO MODE) 1 = 0 means pin positioning is random but it is on equal distance.
priority : system default (floorplanning.tcl) < config.tcl < PDK varient.tcl (sky130A_sky130_fd_sc_hd_congig.tcl)
run_floorplan
cd runs
ls -ltr
cd logs/floorplan
less picorv32a.floorplan.def
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
press S+V - fit layout To Zoom, Left click & Right click & Press Z
Place cursor on object and Press S,open tkcon app and type what
Decap Cells and Tap Cells
Standard Cells at the bottom left
run_placement
cd ../placement
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
standard cells are correctly placed in standard cell rows
Rerun till floorplan
less floorplan.txt
% set ::env(FP_IO_MODE) 2
% run_floorplan
Opening the newly run directory
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &Pins are not equidistant here
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
cd vsdstdcelldesign
Copy the tech file
cd Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic
cp sky130A.tech /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign
magic -T sky130A.tech sky130_inv.mag &
Custom CMOS inverter
Polycross N-diffusion -PMOS
Polycross P-diffusion -NMOS
Y output port connected to PMOS & NMOS
PMOS source connected to VDD
NMOS source connected to VDD
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
gvim sky130_inv.spiceM1000 - Pmos : Drain-Y , Gate-A , Source-VPWR M1001 - Nmos : Drain-Y , Gate-A , Source-VGND
Change scale value,include pmos nmos libraries,add missing connections-VDD,VSS,define input pulse,specify type of analysis
.option scale=0.01u
.include ./libs/pshort.lib
.include ./libs/nshort.lib
//.subckt sky130_inv A Y VPWR VGND
M1001 Y A VGND VGND nshort_model.0 w=35 l=23
+ ad=1.44n pd=0.152m as=1.37n ps=0.148m
M1000 Y A VPWR VPWR pshort_model.0 w=37 l=23
+ ad=1.44n pd=0.152m as=1.52n ps=0.156m
VDD VPWR 0 3.3V
VSS VGND 0 0V
Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)
C0 A Y 0.05fF
C1 Y VPWR 0.11fF
C2 A VPWR 0.07fF
C3 Y 0 0.24fF
C4 VPWR 0 0.59fF
//.ends
.tran 1n 20n
.control
run
.endc
.end
sudo apt-get install ngspice
ngsspice sky130_inv.spic
change in gvim - C3 Y 0 2fF
plot y vs time a
Right click to zoom Rise time transition 20%-0.66 to 80%-2.64 - time value = 60ps
Fall time transition 80%-2.64 to 20%-0.66 - time value = 40ps
Cell rise delay 50%-1.65 - time value = 50ps
Cell fall delay 50%-1.65 - time value = 30ps
wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
tar xfz drc_tests.tgz
cd drc_tests
ls -al
gvim .magicrcmagic -d
magic -d XR &
File -> Open -> met3.mag Sky130 Periphery rules: Link
poly.mag
gvim sky130A.techchange to allpolynonres rule
tech load sky130A.tech
drc check
nwell.mag
% cif ostyle drc
% cif see dnwell_shrink
% feed clear
% cif see nwell_missing
% feed clear
Not a simple edge rule
templayer nwell_tapped
bloat-all nsc nwell
templayer nwell_untapped nwell
and-not nwell_tapped
variants (full)
cifmaxwidth nwell_untapped 0 bend_illegal \
"Nwell missing tap (nwell.4)"
variants *
% tech load sky130A.tech
% drc style drc(full)
% drc check
% drc why
Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd
less tracks.info
help grid
grid 0.46um 0.34um 0.23um 0.17um
Ports lie on the intersection of the vertical and horizontal tracks.Width of the standard cell should be odd multiples of the horizontal track pitch.Height of the standard cell should be even multiples of the vertical track pitch.
Defining ports
save sky130_varun.mag #custom name
lef write
less sky130_varun.lef
Copy necessary files to 'picorv32a' design 'src' directory
cp sky130_varun.lef ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
cp libs/sky130_fd_sc_hd__* ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a
Edit config.tcl to include the added lef and change library to ones we added in src directory
set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]package require openlane 0.9
prep -design picorv32a
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
run_synthesis
Note down values of newly introduced violations with the introduction of custom inverter cell
Stratergy to reduce the violations
prep -design picorv32a -tag 22-04_08-29 -overwrite
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
echo $::env(SYNTH_STRATEGY) # Command to display current value of variable SYNTH_STRATEGY
set ::env(SYNTH_STRATEGY) "DELAY 3" # Command to set new value for SYNTH_STRATEGY
echo $::env(SYNTH_BUFFERING)# Command to display current value of variable SYNTH_BUFFERING to check whether it's enabled
echo $::env(SYNTH_SIZING) # Command to display current value of variable SYNTH_SIZING
set ::env(SYNTH_SIZING) 1 # Command to set new value for SYNTH_SIZING
echo $::env(SYNTH_DRIVING_CELL) # Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not
run_synthesis
Area has increased,Worst negative slack has become 0
run_floorplan
Since we are facing unexpected un-explainable error while using run_floorplan command,run the below instead
init_floorplan
place_io
tap_decap_or
run_placement
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_08-29/results/placement/
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
Since we are having 0 wns after improved timing run we are going to do timing analysis on initial run of synthesis which has lots of violations and no parameters were added to improve timing
Created pre_sta.conf for STA analysis
./flow.tcl -interactive
package require openlane 0.9
prep -design picorv32a
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
set ::env(SYNTH_SIZING) 1
run_synthesis
gvim pre_sta.conf
set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
read_liberty -max /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib
read_liberty -min /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib
read_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_09-28/results/synthesis/picorv32a.synthesis.v
link_design picorv32a
read_sdc /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/my_base.sdc
report_checks -path_delay min_max -fields {slew trans net cap input_pin}
report_tns
report_wnsCreated pre_sta.conf for STA analysis in openlane directory
set ::env(CLOCK_PORT) clk
set ::env(CLOCK_PERIOD) 24.73
#set ::env(SYNTH_DRIVING_CELL) sky130_vsdinv
set ::env(SYNTH_DRIVING_CELL) sky130_fd_sc_hd__inv_8
set ::env(SYNTH_DRIVING_CELL_PIN) Y
set ::env(SYNTH_CAP_LOAD) 17.653
set ::env(IO_PCT) 0.2
set ::env(SYNTH_MAX_FANOUT) 6
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
puts "\[INFO\]: Setting input delay to: $input_delay_value"
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
Created my_base.sdc for STA analysis in openlane/designs/picorv32a/src directory based on the file openlane/scripts/base.sdc
sta pre_sta.conf
Since more fanout is causing more delay we can add parameter to reduce fanout and do synthesis again
prep -design picorv32a -tag 22-04_08-29 -overwrite
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
set ::env(SYNTH_SIZING) 1
set ::env(SYNTH_MAX_FANOUT) 4
echo $::env(SYNTH_DRIVING_CELL)
run_synthesis
Make changes in pre_sta.conf
sta pre_sta.conf
OR gate of drive strength 2 is driving 4 fanouts
Commands to perform analysis and optimize timing by replacing with OR gate of drive strength 4
report_net -connections _11672_
help replace_cell
replace_cell _14510_ sky130_fd_sc_hd__or3_4
report_checks -fields {net cap slew input_pins} -digits 4We observe slack is reduced
Another OR gate of drive strength 2 is driving 4 fanouts
report_net -connections _11675_
replace_cell _14514_ sky130_fd_sc_hd__or3_4
report_checks -fields {net cap slew input_pins} -digits 4We observe slack is reduced again
OR gate of drive strength 2 driving OA gate has more delay
report_net -connections _11643_
replace_cell _14481_ sky130_fd_sc_hd__or4_4
report_checks -fields {net cap slew input_pins} -digits 4We observe slack is reduced again
Another OR gate of drive strength 2 driving OA gate has more delay
report_net -connections _11668_
replace_cell _14506_ sky130_fd_sc_hd__or4_4
report_checks -fields {net cap slew input_pins} -digits 4We observe slack is reduced again
Verify instance 14506 is replaced with sky130_fd_sc_hd__or4_4
report_checks -from _29043_ -to _30440_ -through _14506_
Around 1.2827 ns of violation reduced.
Replace the old netlist with the new netlist generated after timing ECO fix and implement the floorplan, placement and cts.
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/ 22-04_08-29/results/synthesis/
ls
cp picorv32a.synthesis.v picorv32a.synthesis_old.v
ls
help write_verilog
write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_08-29/results/synthesis/picorv32a.synthesis.v
exit
Verified that the netlist is overwritten by checking that instance 14506 is replaced with sky130_fd_sc_hd__or4_4
Since we confirmed that netlist is replaced and will be loaded in PnR but since we want to follow up on the earlier 0 violation design we are continuing with the clean design to further stages
prep -design picorv32a -tag 22-04_08-29 -overwrite
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
set ::env(SYNTH_STRATEGY) "DELAY 3"
set ::env(SYNTH_SIZING) 1
run_synthesis
init_floorplan
place_io
tap_decap_or
run_placement
run_cts
echo $::env(LIB_SYNTH_COMPLETE)
echo $::env(LIB_TYPICAL)
echo $::env(CURRENT_DEF)
echo $::env(SYNTH_MAX_TRAN)
echo $::env(CTS_MAX_CAP)
echo $::env(CTS_CLK_BUFFER_LIST)
echo $::env(CTS_ROOT_BUFFER)
openroad
read_lef /openLANE_flow/designs/picorv32a/runs/22-04_08-29/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/22-04_08-29/results/cts/picorv32a.cts.lef
write_db pico_cts.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/22-04_08-29/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
help report_checks
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
exit
This analysis is incorrect
echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
echo $::env(CTS_CLK_BUFFER_LIST)
echo $::env(CURRENT_DEF)
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/22-04_08-29/results/placement/picorv32a.placement.def
run_cts
echo $::env(CTS_CLK_BUFFER_LIST)
openroad
read_lef /openLANE_flow/designs/picorv32a/runs/22-04_08-29/tmp/merged.lef
read_def /openLANE_flow/designs/picorv32a/runs/22-04_08-29/results/cts/picorv32a.cts.def
write_db pico_cts1.db
read_db pico_cts.db
read_verilog /openLANE_flow/designs/picorv32a/runs/22-04_08-29/results/synthesis/picorv32a.synthesis_cts.v
read_liberty $::env(LIB_SYNTH_COMPLETE)
link_design picorv32a
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
set_propagated_clock [all_clocks]
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
report_clock_skew -hold
report_clock_skew -setup
exit
echo $::env(CTS_CLK_BUFFER_LIST)
set ::env(CTS_CLK_BUFFER_LIST) [linsert $::env(CTS_CLK_BUFFER_LIST) 0 sky130_fd_sc_hd__clkbuf_1]
echo $::env(CTS_CLK_BUFFER_LIST)
gen_pdn
Load PDN def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_08-29/tmp/floorplan/
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read 19-pdn.def &
echo $::env(CURRENT_DEF)
run_routing
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_08-29/results/routing/
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/22-04_08-29/tmp/routing
gvim 20-fastroute.guide
Final generated layout
https://futureskillsprime.in/course/digital-vlsi-soc-design-and-planning
Repo Documentation format inspired from Ms.Kalpana , Mr.Mohammed Fayiz Ferosh
Dear Kunal Ghosh, Nickson P Jose, and R. Timothy Edwards,
I want to express my heartfelt gratitude to each of you for your invaluable contributions and dedication during the workshop. Your expertise, guidance, and passion for teaching have truly made a significant impact on me.Thank you for your time, energy, and commitment to nurturing the next generation of engineers.
With deep appreciation,
Varun
