Table of Contents
This project aims to interface different Peripherals, Memory integrated with RISC-V(Reduced Instruction Set Computer) processor and successfully implement it on FPGA.
FemtoRV is a minimalistic RISC-V design, with easy-to-read Verilog sources directly written from the RISC-V specification. The most elementary version (quark), an RV32I core, weights 400 lines of VERILOG (documented version), and 100 lines if you remove the comments. We will be using FemtoRV32 quark version for our SoC.
Simulation is the process of creating models that mimic the behavior of the device you are designing (simulation models) and creating models to exercise the device (test benches)
- Icarus Verilog is an implementation of the Verilog hardware description language.
- GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing.
Installing iverilog and gtwave for Ubuntu
$ sudo apt-get install iverilog
$ sudo apt-get install gtkwave
To simulate and run the verilog code, follow the format:
$ iverilog example.v example_tb.v
This command compiles the design, which is spread across two input files. This works for small to medium sized designs. Next execute the compiled program like so:
$ vvp a.out
To see the output waveform on gtkwave
$ gtkwave dumpfile_name.vcd
Synthesis converts a basic RTL (Register Transfer Logic) design into a gate-level netlist that includes all of the designer's limitations.
Yosys is a framework for Verilog RTL synthesis
To install yosys follow the instructions mentioned in this repo : Yosys Open SYnthesis Suite
Now simply run yosys_run.sh file, to synthesize:
yosys -s yosys_run.sh
GLS is generating the simulation output by running test bench with netlist file generated from synthesis tool as design under test. Netlist is logically same as RTL code, therefore, same testbench can be used for it. We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met.
run the following command format to perform GLS simulation:
$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#0 ../top_module_directory/verilog_model/primitives.v ../top_module_directory/verilog_model/sky130_
fd_sc_hd.v my_design_synth.v example_tb.v
$ ./a.out
$ gtkwave dumpfile_name.vcd
One will observe that the gtkwave waveform for the netlist should match the waveform to that of the RTL-design given the same testbench.
A UART ( Universal Asynchronous Receiver Transmitter ) is a device-to-device hardware communication protocol that uses asynchronous serial communication with configurable speed.
SPI is a synchronous, full duplex main-subnode-based interface. The data from the main or the subnode is synchronized on the rising or falling clock edge. Both main and subnode can transmit data at the same time. The SPI interface can be either 3-wire or 4-wire.
Image courtesy: Analog Devices
Integrating a Synchronous Dynamic Random Access Memory (SDRAM) with a RISC-V processor typically involves designing a memory controller that interfaces with the SDRAM and communicates with the processor through a bus interface. The memory controller manages the flow of data between the processor and the SDRAM, handling tasks such as address decoding, read and write operations, and refresh cycles.
The WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. This is accomplished by creating a common interface between IP cores. This improves the portability and reliability of the system, and results in faster time-to-market for the end use.