MIPS-CPU

Extension version of TinyMIPS processor, which is an implementation of for USTB computer composition principle course design.

MIPS-CPU's ISA

1. 算术运算指令

• ADD 2021-2-21 1
• ADDI 2021-2-21 2
• ADDU
• ADDIU
• SUB 2021-2-21 3
• SUBU
• SLT
• SLTI 2021-2-21 4
• SLTU
• SLTIU 2021-2-21 5
• DIV 2021-2-24 5
• DIVU 2021-2-24 6
• MULT 2021-2-24 7
• MULTU 2021-2-24 8

2. 逻辑运算指令

• AND
• ANDI 2021-2-21 6
• LUI
• NOR 2021-2-21 7
• OR
• ORI 2021-2-21 8
• XOR
• XORI 2021-2-21 9

3. 移位指令

• SLL
• SLLV
• SRA 2021-2-21 10
• SRAV
• SRL 2021-2-21 11
• SRLV

4. 分支跳转指令

• BEQ
• BNE
• BGEZ 2021-2-22 3
• BLTZ 2021-2-22 4
• BLTZAL 2021-2-22 5
• BGEZAL 2021-2-22 6
• BGTZ 2021-2-22 1
• BLEZ 2021-2-22 2
• J 2021-2-22 7
• JAL
• JR 2021-2-22 8
• JALR

5. 访存指令

• LB
• LBU
• LH 2021-2-22 9
• LHU 2021-2-22 10
• LW
• LWL 2021-2-23 1
• LWR 2021-2-23 2
• SB
• SH 2021-2-22 11
• SW
• SWL 2021-2-23 3
• SWR 2021-2-23 4

6. 数据移动指令

• MFHI 2021-2-24 1
• MFLO 2021-2-24 2
• MTHI 2021-2-24 3
• MTLO 2021-2-24 4

7. 自陷指令

• BREAK 2021-2-24 9
• SYSCALL 2021-2-24 10

8. 特权指令

• ERET 2021-2-24 11
• MFC0 2021-2-24 12
• MTC0 2021-2-24 13

MIPS-CPU's Design