docs: no need for PrintGenFiles = true due to scastie special-casing

DFiantHDL · Aug 27, 2024 · 5d3a14c · 5d3a14c
1 parent b842c97
commit 5d3a14c
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Showing 8 changed files with 0 additions and 16 deletions.
diff --git a/lib/src/test/scala/docExamples/ALU.scala b/lib/src/test/scala/docExamples/ALU.scala
@@ -35,8 +35,6 @@ end ALU
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/Blinker.scala b/lib/src/test/scala/docExamples/Blinker.scala
@@ -30,8 +30,6 @@ end Blinker
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/Counter.scala b/lib/src/test/scala/docExamples/Counter.scala
@@ -19,8 +19,6 @@ import dfhdl.* //import all the DFHDL goodness
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/FullAdder1.scala b/lib/src/test/scala/docExamples/FullAdder1.scala
@@ -14,8 +14,6 @@ import dfhdl.* //import all the DFHDL goodness
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.vhdl
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/FullAdderN.scala b/lib/src/test/scala/docExamples/FullAdderN.scala
@@ -31,8 +31,6 @@ end FullAdderN
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/RegFile.scala b/lib/src/test/scala/docExamples/RegFile.scala
@@ -32,8 +32,6 @@ end RegFile
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/TrueDPR.scala b/lib/src/test/scala/docExamples/TrueDPR.scala
@@ -30,8 +30,6 @@ end TrueDPR
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation:

diff --git a/lib/src/test/scala/docExamples/UART_Tx.scala b/lib/src/test/scala/docExamples/UART_Tx.scala
@@ -82,8 +82,6 @@ end UART_Tx
 ////////////////////////////////////////////////////////////////////////////////////////////////
 // Select backend compiler:
 given options.CompilerOptions.Backend = backends.verilog
-// Enables printing the generated chosen backend code:
-given options.CompilerOptions.PrintGenFiles = true
 // Uncomment to enable printing design code after elaboration (before compilation):
 // given options.ElaborationOptions.PrintDesignCodeAfter = true
 // Uncomment to enable printing design code after compilation: