Merge pull request #130 from DFiantHDL/i129

Fix #129

compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLPrinter.scala

@@ -66,6 +66,7 @@ class VHDLPrinter(using val getSet: MemberGetSet, val printerOptions: PrinterOpt
        |function to_slv(A : unsigned) return std_logic_vector;
        |function to_slv(A : signed) return std_logic_vector;
        |function to_slv(A : boolean) return std_logic_vector;
+       |function to_slv(A : std_logic) return std_logic_vector;
        |function to_sl(b : boolean) return std_logic;
        |function to_bool(sl : std_logic) return boolean;
        |function resize(A : std_logic_vector; new_length : integer) return std_logic_vector;
@@ -118,6 +119,14 @@ class VHDLPrinter(using val getSet: MemberGetSet, val printerOptions: PrinterOpt
        |    return "0";
        |  end if;
        |end;
+       |function to_slv(A : std_logic) return std_logic_vector is
+       |begin
+       |  if A = '1' then 
+       |    return "1";
+       |  else
+       |    return "0";
+       |  end if;
+       |end;
        |function to_sl(b : boolean) return std_logic is
        |begin
        |  if (b) then

lib/src/test/scala/issues/IssueSpec.scala

@@ -12,3 +12,6 @@ class IssuesSpec extends FunSuite:
   test("i126 compiles and passes VHDL linting"):
     given options.CompilerOptions.Backend = backends.vhdl
     i126.TypeConvertIssue().compile.lint
+  test("i129 compiles and passes VHDL linting"):
+    given options.CompilerOptions.Backend = backends.vhdl
+    i129.StdLogicConvIssue().compile.lint

lib/src/test/scala/issues/i129.scala

@@ -0,0 +1,11 @@
+// format: off
+package issues.i129
+
+import dfhdl.*
+
+class StdLogicConvIssue() extends RTDesign:
+    val a = Bits(10) <> IN
+    val e = Bits(10) <> OUT
+
+    e := (a(0), a(3), b"0", false.bit, b"000000")
+