fix vhdl to_slv for vectors with depth > 1

DFiantHDL · Oct 9, 2024 · 156cd71 · 156cd71
1 parent 56e8bd8
commit 156cd71
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLTypePrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLTypePrinter.scala
@@ -222,7 +222,7 @@ protected trait VHDLTypePrinter extends AbstractTypePrinter:
           |function to_slv(A : ${typeName}) return std_logic_vector;
           |function to_${typeName}(A : std_logic_vector$dimArgs$cellDimArg) return ${typeName};
           |function bool_sel(C : boolean; T : ${typeName}; F : ${typeName}) return ${typeName};""".stripMargin
-    val toSLV = printer.csToSLV(vecType.cellType, "A(i)")
+    val toSLV = if (depth == 1) printer.csToSLV(vecType.cellType, "A(i)") else "to_slv(A(i))"
     val dims = act(
       _ => "",
       depth => (depth to 1 by -1).map(i => s"(0 to D$i - 1)").mkString