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<span class="k"><span class="pre">ENTITY</span> </span><span class="sig-name descname"><span class="pre">SR_SYNC_LATCH</span></span><span class="k"> <span class="pre">IS</span></span><a class="headerlink" href="#vhdl-entity-sr_sync_latch" title="Link to this definition"></a></dt>
<dd><p>This component provides synchrnous SR latch behavior with some enhancements:</p>
<p>1. The forbidden state when both <a class="reference internal" href="#vhdl-portsignal-sr_sync_latch-set"><code class="xref vhdl vhdl-portsignal docutils literal notranslate"><span class="pre">SET</span></code></a> and
<a class="reference internal" href="../../dsp/dsp_comparator/readme.html#vhdl-portsignal-dsp_comparator-reset"><code class="xref vhdl vhdl-portsignal docutils literal notranslate"><span class="pre">RESET</span></code></a> are asserted has been removed.
<a class="reference internal" href="#vhdl-portsignal-sr_sync_latch-reset"><code class="xref vhdl vhdl-portsignal docutils literal notranslate"><span class="pre">RESET</span></code></a> are asserted has been removed.
In this case, the design
behaves in the same way when both signals are deasserted, e.g. it keeps its
output unchanged.</p>
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