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MAC_LITE UVM: [MAITENANCE] change logic for checking if design is blo…
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…cked
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radek-isa committed Aug 24, 2023
1 parent 0e6038e commit 8074c59
Showing 1 changed file with 6 additions and 15 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@ class base extends uvm_test;
/////////////////////
// variables
uvm_mac_seg_rx::env#(SEGMENTS, REGIONS, REGION_SIZE) m_env;
bit timeout;

/////////////////////
// functions
Expand All @@ -30,15 +29,9 @@ class base extends uvm_test;
#(time_length*1us);
endtask

task test_wait_result();
do begin
#(600ns);
end while (m_env.sc.used() != 0);
timeout = 0;
endtask

//run virtual sequence on virtual sequencer
virtual task run_phase(uvm_phase phase);
time time_start;
uvm_mac_seg_rx::sequence_simple_1 seq;

uvm_component c;
Expand All @@ -53,18 +46,16 @@ class base extends uvm_test;
seq.randomize();
seq.start(m_env.m_sequencer);

timeout = 1;
fork
test_wait_timeout(20);
test_wait_result();
join_any;

time_start = $time();
while ((time_start + 20us) > $time() && m_env.sc.used() != 0) begin
#(600ns);
end
phase.drop_objection(this);
endtask

function void report_phase(uvm_phase phase);
`uvm_info(this.get_full_name(), {"\n\tTEST : ", this.get_type_name(), " END\n"}, UVM_NONE);
if (timeout) begin
if (m_env.sc.used() != 0) begin
`uvm_error(this.get_full_name(), "\n\t===================================================\n\tTIMEOUT SOME PACKET STUCK IN DESIGN\n\t===================================================\n\n");
end
endfunction
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