Merge branch 'gurka-feat-xbuild' into 'main'

Add prototype of unified build script See merge request ndk/ofm!398
CESNET · Sep 5, 2024 · 339d7af · 339d7af
2 parents d7a1934 + 1540fca
commit 339d7af
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diff --git a/build/Modelsim.inc.fdo b/build/Modelsim.inc.fdo
@@ -427,7 +427,24 @@ proc nb_sim_parse_parameters {sim_flags} {
     echo "============================"
 }
 
-proc nb_sim_main {{user_sim_flags SIM_FLAGS}} {
+proc nb_sim_expand_generics {{vsim_flags VSIM_FLAGS} {sim_flags SIM_FLAGS}} {
+    upvar 1 $vsim_flags VSIM_FLAGS
+    upvar 1 $sim_flags SIM_FLAGS
+
+    if {[file exists "./tmp/generics.fdo"]} {
+        source "./tmp/generics.fdo"
+        puts "HARP: Found file with entity parameters settings."
+    } else {
+        return
+    }
+
+    foreach {key value} [array get SIM_GENERICS] {
+        puts "$key=$value"
+        lappend VSIM_FLAGS "-g$SIM_FLAGS(SIM_MODULE)/$key=$value"
+    }
+}
+
+proc nb_sim_main {{user_sim_flags SIM_FLAGS} {sim_generics SIM_GENERICS}} {
     # Let VSIM_FLAGS variable to be accessible in top level stack frame for running vsim by hand
     upvar 1 VSIM_FLAGS VSIM_FLAGS
 
@@ -448,7 +465,10 @@ proc nb_sim_main {{user_sim_flags SIM_FLAGS}} {
 
     nb_vsim_prepare
     nb_vsim_compile_project SIM_FLAGS HIERARCHY
+
     nb_vsim_set_flags VSIM_FLAGS SIM_FLAGS
+    nb_sim_expand_generics VSIM_FLAGS SIM_FLAGS
+
 
     # Run simulation
     if {!$SIM_FLAGS(VSIM_MANUAL_START)} {

diff --git a/comp/mfb_tools/flow/pipe/harp.toml b/comp/mfb_tools/flow/pipe/harp.toml
@@ -0,0 +1,64 @@
+# rtlproject.toml: File verification and synthesis combinations
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Oliver Gurka <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+[settings.default]
+REGIONS     = 4
+REGION_SIZE = 8
+BLOCK_SIZE  = 8
+ITEM_WIDTH  = 8
+FAKE_PIPE   = false
+USE_DST_RDY = true
+PIPE_TYPE   = "SHREG"
+DEVICE      = "ULTRASCALE"
+
+[settings.regions]
+type = "list"
+REGIONS     = [1, 2, 1, 1, 1, 1]
+REGION_SIZE = [8, 8, 1, 2, 2, 4]
+BLOCK_SIZE  = [8, 8, 8, 8, 4, 8]
+ITEM_WIDTH  = [8, 8, 8, 8, 8, 8]
+
+[settings.pcie]
+REGIONS     = 2
+REGION_SIZE = 1
+BLOCK_SIZE  = 8
+ITEM_WIDTH  = 32
+
+[settings.pipe_type_reg]
+PIPE_TYPE = "REG"
+
+[settings.fake_pipe_up]
+FAKE_PIPE = true
+
+[settings.use_dst_rdy_down]
+USE_DST_RDY = false
+
+[[ver.combinations]]
+name = "haha"
+settings = ["regions"]
+
+[[ver.combinations]]
+name = "haha1"
+settings = ["regions", "fake_pipe_up"]
+
+[[ver.combinations]]
+name = "haha2"
+settings = ["regions[4:6]", "use_dst_rdy_down"]
+
+[[ver.combinations]]
+name = "haha3"
+settings = ["pcie", ["fake_pipe_up", "use_dst_rdy_down"]]
+
+[[ver.combinations]]
+name = "haha4"
+settings = ["", ["fake_pipe_up", "use_dst_rdy_down", "pipe_type_reg"]]
+
+[ver.settings]
+tests = ["ex_test"]
+
+[[synth.combinations]]
+name = "dfasd"
+settings = ["regions"]
diff --git a/comp/mvb_tools/flow/mvb2mfb/harp.toml b/comp/mvb_tools/flow/mvb2mfb/harp.toml
@@ -0,0 +1,56 @@
+# rtlproject.toml: File verification and synthesis combinations
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Oliver Gurka <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+[generics]
+asserts = [
+    """(MVB_ITEM_WIDTH_RAW >= MFB_REGION_SIZE * MFB_BLOCK_SIZE * MFB_ITEM_WIDTH) \
+    or (MFB_ALIGNMENT == MFB_REGION_SIZE * MFB_BLOCK_SIZE)""",
+    "(MVB_ITEM_WIDTH_RAW % MFB_ITEM_WIDTH) == 0",
+    """(MFB_ALIGNMENT <= MFB_REGION_SIZE*MFB_BLOCK_SIZE) and \
+    (MFB_ALIGNMENT >= MFB_BLOCK_SIZE)""",
+]
+
+[settings.default]
+MFB_REGIONS         = 4
+MFB_REGION_SIZE     = 8
+MFB_BLOCK_SIZE      = 8
+MFB_ITEM_WIDTH      = 8
+MFB_ALIGNMENT       = 64
+MFB_META_WIDTH      = 12
+DEVICE              = "ULTRASCALE"
+MVB_ITEMS           = 4
+MVB_ITEM_WIDTH_RAW  = 536
+
+[settings.regions]
+type = "list"
+MVB_ITEMS   = [1, 2]
+MFB_REGIONS = [1, 2]
+
+[settings.align_low]
+MFB_ALIGNMENT = 8
+
+[settings.mvb_item_small]
+MVB_ITEM_WIDTH_RAW = 48
+
+[[ver.combinations]]
+name = "regions"
+settings = ["regions"]
+
+[[ver.combinations]]
+name = "small"
+settings = ["", ["align_low", "mvb_item_small"]]
+
+[[ver.combinations]]
+name = "region_big_small"
+settings = ["regions[0]", ["mvb_item_small", "align_low"]]
+
+[ver.settings]
+tests = ["test_basic", "test_perf"]
+
+[[synth.combinations]]
+name        = "Some basic"
+description = "Space search of resource usage and timing for Agilex and Ultrascale devices"
+settings    = ["regions"]
diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/dut.sv b/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/dut.sv
@@ -4,10 +4,18 @@
 
 // SPDX-License-Identifier: BSD-3-Clause
 
-
-import test::*;
-
-module DUT (
+module DUT #(
+    int unsigned MVB_ITEMS,
+    int unsigned MVB_ITEM_WIDTH_RAW,
+    int unsigned MFB_REGIONS,
+    int unsigned MFB_REGION_SIZE,
+    int unsigned MFB_BLOCK_SIZE,
+    int unsigned MFB_ITEM_WIDTH,
+    int unsigned MFB_ALIGNMENT,
+    int unsigned MFB_META_WIDTH,
+    int unsigned MVB_ITEM_WIDTH,
+    string DEVICE
+) (
     input logic     CLK,
     input logic     RST,
     mvb_if.dut_rx   mvb_rx,

diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/testbench.sv b/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/testbench.sv
@@ -9,11 +9,24 @@ import uvm_pkg::*;
 `include "uvm_macros.svh"
 import test::*;
 
-module testbench;
+module testbench #(
+    int unsigned MVB_ITEMS,
+    int unsigned MVB_ITEM_WIDTH_RAW,
+    int unsigned MFB_REGIONS,
+    int unsigned MFB_REGION_SIZE,
+    int unsigned MFB_BLOCK_SIZE,
+    int unsigned MFB_ITEM_WIDTH,
+    int unsigned MFB_ALIGNMENT,
+    int unsigned MFB_META_WIDTH,
+    string DEVICE
+);
+
+    localparam int unsigned MVB_ITEM_WIDTH = MVB_ITEM_WIDTH_RAW+MFB_META_WIDTH;
 
     //TESTS
-    typedef test::ex_test ex_test;
-    typedef test::speed speed;
+    typedef test::ex_test #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) ex_test;
+    typedef test::speed #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) speed;
+
 
     // -------------------------------------------------------------------------------------------------------------------------------------------------------------------
     // Signals
@@ -53,7 +66,18 @@ module testbench;
 
     // -------------------------------------------------------------------------------------------------------------------------------------------------------------------
     // DUT
-    DUT DUT_U (
+    DUT #(
+        .MVB_ITEMS          (MVB_ITEMS),
+        .MVB_ITEM_WIDTH_RAW (MVB_ITEM_WIDTH_RAW),
+        .MFB_REGIONS        (MFB_REGIONS),
+        .MFB_REGION_SIZE    (MFB_REGION_SIZE),
+        .MFB_BLOCK_SIZE     (MFB_BLOCK_SIZE),
+        .MFB_ITEM_WIDTH     (MFB_ITEM_WIDTH),
+        .MFB_ALIGNMENT      (MFB_ALIGNMENT),
+        .MFB_META_WIDTH     (MFB_META_WIDTH),
+        .MVB_ITEM_WIDTH     (MVB_ITEM_WIDTH),
+        .DEVICE             (DEVICE)
+    ) DUT_U (
         .CLK        (CLK),
         .RST        (reset.RESET),
         .mvb_rx     (mvb_rx),

diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/pkg.sv b/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/pkg.sv
@@ -13,19 +13,6 @@ package test;
     `include "uvm_macros.svh"
     import uvm_pkg::*;
 
-    parameter MFB_REGIONS        = 1;
-    parameter MFB_REGION_SIZE    = 8;
-    parameter MFB_BLOCK_SIZE     = 8;
-    parameter MFB_ITEM_WIDTH     = 8;
-    parameter MFB_META_WIDTH     = 12;
-
-    parameter MVB_ITEMS          = 1;
-    parameter MVB_ITEM_WIDTH_RAW = 48;
-    parameter MVB_ITEM_WIDTH     = MVB_ITEM_WIDTH_RAW+MFB_META_WIDTH;
-
-    parameter MFB_ALIGNMENT      = MFB_REGION_SIZE*MFB_BLOCK_SIZE;
-    parameter DEVICE             = "ULTRASCALE";
-
     parameter CLK_PERIOD         = 4ns;
     parameter RESET_CLKS         = 10;
 

diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/speed.sv b/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/speed.sv
@@ -37,8 +37,8 @@ class mfb_rx_speed#(MFB_REGIONS, MFB_REGION_SIZE, MFB_ITEM_WIDTH, MFB_BLOCK_SIZE
     endfunction
 endclass
 
-class speed extends uvm_test;
-     typedef uvm_component_registry#(test::speed, "test::speed") type_id;
+class speed #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) extends uvm_test;
+     typedef uvm_component_registry#(test::speed #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH), "test::speed") type_id;
 
     // declare the Environment reference variable
     uvm_mvb2mfb::env #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) m_env;

diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/test.sv b/comp/mvb_tools/flow/mvb2mfb/uvm/tbench/tests/test.sv
@@ -4,8 +4,8 @@
 
 // SPDX-License-Identifier: BSD-3-Clause
 
-class ex_test extends uvm_test;
-    typedef uvm_component_registry#(test::ex_test, "test::ex_test") type_id;
+class ex_test #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) extends uvm_test;
+    typedef uvm_component_registry#(test::ex_test #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH), "test::ex_test") type_id;
 
     // declare the Environment reference variable
     uvm_mvb2mfb::env #(MFB_REGIONS, MVB_ITEMS, MFB_REGION_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MFB_META_WIDTH, MVB_ITEM_WIDTH) m_env;

diff --git a/comp/mvb_tools/flow/mvb2mfb/uvm/top_level.fdo b/comp/mvb_tools/flow/mvb2mfb/uvm/top_level.fdo
@@ -22,9 +22,16 @@ set SIM_FLAGS(CODE_COVERAGE) false
 
 set SIM_FLAGS(UVM_ENABLE) true
 set SIM_FLAGS(UVM_TEST) "test::ex_test"
+set SIM_FLAGS(DEBUG) true
 #set SIM_FLAGS(UVM_TEST) "test::speed"
 set SIM_FLAGS(UVM_VERBOSITY) UVM_NONE
 
+if {[file exists "./generics.fdo"]} {
+    source "./generics.fdo"
+} else {
+    puts "Could not source generics.fdo."
+}
+
 # Global include file for compilation
 source "$FIRMWARE_BASE/build/Modelsim.inc.fdo"