From e749bb0923f0571ee897fe1f75808de7b0d1753d Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 2 Aug 2024 13:16:06 +0800 Subject: [PATCH] Let MXR not affect implicit memory access for VS-stage address translation The behavior of MXR is clarified in https://github.com/riscv/riscv-isa-manual/pull/1543. --- riscv/mmu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 94997a23e..ffbe66dce 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -404,7 +404,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty int maxgpabits = vm.levels * vm.idxbits + vm.widenbits + PGSHIFT; reg_t maxgpa = (1ULL << maxgpabits) - 1; - bool mxr = proc->state.sstatus->readvirt(false) & MSTATUS_MXR; + bool mxr = !is_for_vs_pt_addr && (proc->state.sstatus->readvirt(false) & MSTATUS_MXR); // tinst is set to 0x3000/0x3020 - for RV64 read/write respectively for // VS-stage address translation (for spike HSXLEN == VSXLEN always) else // tinst is set to 0x2000/0x2020 - for RV32 read/write respectively for