From 45da44e7f177fc34d1a3a1b804d1bc12e2c467f9 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 14 Dec 2023 06:56:00 -0800 Subject: [PATCH] Correct/improve some field descriptions for ESP32-S3's `LCD_CAM` peripheral --- esp32s3/src/lcd_cam/cam_ctrl.rs | 16 ++++++------ esp32s3/src/lcd_cam/cam_ctrl1.rs | 28 ++++++++++---------- esp32s3/src/lcd_cam/lcd_clock.rs | 8 +++--- esp32s3/src/lcd_cam/lcd_user.rs | 44 ++++++++++++++++---------------- esp32s3/svd/patches/esp32s3.yaml | 41 +++++++++++++++++++++++++++++ 5 files changed, 89 insertions(+), 48 deletions(-) diff --git a/esp32s3/src/lcd_cam/cam_ctrl.rs b/esp32s3/src/lcd_cam/cam_ctrl.rs index afc22ff818..bdd547ffb4 100644 --- a/esp32s3/src/lcd_cam/cam_ctrl.rs +++ b/esp32s3/src/lcd_cam/cam_ctrl.rs @@ -14,13 +14,13 @@ pub type CAM_VSYNC_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; pub type CAM_UPDATE_R = crate::BitReader; #[doc = "Field `CAM_UPDATE` writer - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."] pub type CAM_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CAM_BYTE_ORDER` reader - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +#[doc = "Field `CAM_BYTE_ORDER` reader - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."] pub type CAM_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `CAM_BYTE_ORDER` writer - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +#[doc = "Field `CAM_BYTE_ORDER` writer - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."] pub type CAM_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CAM_BIT_ORDER` reader - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +#[doc = "Field `CAM_BIT_ORDER` reader - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."] pub type CAM_BIT_ORDER_R = crate::BitReader; -#[doc = "Field `CAM_BIT_ORDER` writer - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +#[doc = "Field `CAM_BIT_ORDER` writer - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."] pub type CAM_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CAM_LINE_INT_EN` reader - 1: Enable to generate CAM_HS_INT. 0: Disable."] pub type CAM_LINE_INT_EN_R = crate::BitReader; @@ -62,12 +62,12 @@ impl R { pub fn cam_update(&self) -> CAM_UPDATE_R { CAM_UPDATE_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[doc = "Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."] #[inline(always)] pub fn cam_byte_order(&self) -> CAM_BYTE_ORDER_R { CAM_BYTE_ORDER_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[doc = "Bit 6 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."] #[inline(always)] pub fn cam_bit_order(&self) -> CAM_BIT_ORDER_R { CAM_BIT_ORDER_R::new(((self.bits >> 6) & 1) != 0) @@ -173,13 +173,13 @@ impl W { pub fn cam_update(&mut self) -> CAM_UPDATE_W { CAM_UPDATE_W::new(self, 4) } - #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[doc = "Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change."] #[inline(always)] #[must_use] pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W { CAM_BYTE_ORDER_W::new(self, 5) } - #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[doc = "Bit 6 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in 8-bit mode, and bits\\[15:0\\] to bits\\[0:15\\] in 16-bit mode. 0: Do not change."] #[inline(always)] #[must_use] pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W { diff --git a/esp32s3/src/lcd_cam/cam_ctrl1.rs b/esp32s3/src/lcd_cam/cam_ctrl1.rs index a18aaa6a90..5905239e77 100644 --- a/esp32s3/src/lcd_cam/cam_ctrl1.rs +++ b/esp32s3/src/lcd_cam/cam_ctrl1.rs @@ -2,13 +2,13 @@ pub type R = crate::R; #[doc = "Register `CAM_CTRL1` writer"] pub type W = crate::W; -#[doc = "Field `CAM_REC_DATA_BYTELEN` reader - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] +#[doc = "Field `CAM_REC_DATA_BYTELEN` reader - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."] pub type CAM_REC_DATA_BYTELEN_R = crate::FieldReader; -#[doc = "Field `CAM_REC_DATA_BYTELEN` writer - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] +#[doc = "Field `CAM_REC_DATA_BYTELEN` writer - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."] pub type CAM_REC_DATA_BYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `CAM_LINE_INT_NUM` reader - The line number minus 1 to generate cam_hs_int."] +#[doc = "Field `CAM_LINE_INT_NUM` reader - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."] pub type CAM_LINE_INT_NUM_R = crate::FieldReader; -#[doc = "Field `CAM_LINE_INT_NUM` writer - The line number minus 1 to generate cam_hs_int."] +#[doc = "Field `CAM_LINE_INT_NUM` writer - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."] pub type CAM_LINE_INT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `CAM_CLK_INV` reader - 1: Invert the input signal CAM_PCLK. 0: Not invert."] pub type CAM_CLK_INV_R = crate::BitReader; @@ -18,9 +18,9 @@ pub type CAM_CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>; pub type CAM_VSYNC_FILTER_EN_R = crate::BitReader; #[doc = "Field `CAM_VSYNC_FILTER_EN` writer - 1: Enable CAM_VSYNC filter function. 0: bypass."] pub type CAM_VSYNC_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CAM_2BYTE_EN` reader - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] +#[doc = "Field `CAM_2BYTE_EN` reader - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."] pub type CAM_2BYTE_EN_R = crate::BitReader; -#[doc = "Field `CAM_2BYTE_EN` writer - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] +#[doc = "Field `CAM_2BYTE_EN` writer - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."] pub type CAM_2BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CAM_DE_INV` reader - CAM_DE invert enable signal, valid in high level."] pub type CAM_DE_INV_R = crate::BitReader; @@ -44,15 +44,15 @@ pub type CAM_START_R = crate::BitReader; pub type CAM_START_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CAM_RESET` writer - Camera module reset signal."] pub type CAM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CAM_AFIFO_RESET` writer - Camera AFIFO reset signal."] +#[doc = "Field `CAM_AFIFO_RESET` writer - Camera Async Rx FIFO reset signal."] pub type CAM_AFIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] + #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."] #[inline(always)] pub fn cam_rec_data_bytelen(&self) -> CAM_REC_DATA_BYTELEN_R { CAM_REC_DATA_BYTELEN_R::new((self.bits & 0xffff) as u16) } - #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."] + #[doc = "Bits 16:21 - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."] #[inline(always)] pub fn cam_line_int_num(&self) -> CAM_LINE_INT_NUM_R { CAM_LINE_INT_NUM_R::new(((self.bits >> 16) & 0x3f) as u8) @@ -67,7 +67,7 @@ impl R { pub fn cam_vsync_filter_en(&self) -> CAM_VSYNC_FILTER_EN_R { CAM_VSYNC_FILTER_EN_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] + #[doc = "Bit 24 - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."] #[inline(always)] pub fn cam_2byte_en(&self) -> CAM_2BYTE_EN_R { CAM_2BYTE_EN_R::new(((self.bits >> 24) & 1) != 0) @@ -143,13 +143,13 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] + #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."] #[inline(always)] #[must_use] pub fn cam_rec_data_bytelen(&mut self) -> CAM_REC_DATA_BYTELEN_W { CAM_REC_DATA_BYTELEN_W::new(self, 0) } - #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."] + #[doc = "Bits 16:21 - Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered."] #[inline(always)] #[must_use] pub fn cam_line_int_num(&mut self) -> CAM_LINE_INT_NUM_W { @@ -167,7 +167,7 @@ impl W { pub fn cam_vsync_filter_en(&mut self) -> CAM_VSYNC_FILTER_EN_W { CAM_VSYNC_FILTER_EN_W::new(self, 23) } - #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] + #[doc = "Bit 24 - 1: The width of input data is 16 bits. 0: The width of input data is 8 bits."] #[inline(always)] #[must_use] pub fn cam_2byte_en(&mut self) -> CAM_2BYTE_EN_W { @@ -209,7 +209,7 @@ impl W { pub fn cam_reset(&mut self) -> CAM_RESET_W { CAM_RESET_W::new(self, 30) } - #[doc = "Bit 31 - Camera AFIFO reset signal."] + #[doc = "Bit 31 - Camera Async Rx FIFO reset signal."] #[inline(always)] #[must_use] pub fn cam_afifo_reset(&mut self) -> CAM_AFIFO_RESET_W { diff --git a/esp32s3/src/lcd_cam/lcd_clock.rs b/esp32s3/src/lcd_cam/lcd_clock.rs index 0696321f9d..22ae501ce1 100644 --- a/esp32s3/src/lcd_cam/lcd_clock.rs +++ b/esp32s3/src/lcd_cam/lcd_clock.rs @@ -34,9 +34,9 @@ pub type LCD_CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; pub type LCD_CLK_SEL_R = crate::FieldReader; #[doc = "Field `LCD_CLK_SEL` writer - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] pub type LCD_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CLK_EN` reader - Set this bit to enable clk gate"] +#[doc = "Field `CLK_EN` reader - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."] pub type CLK_EN_R = crate::BitReader; -#[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"] +#[doc = "Field `CLK_EN` writer - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."] pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."] @@ -79,7 +79,7 @@ impl R { pub fn lcd_clk_sel(&self) -> LCD_CLK_SEL_R { LCD_CLK_SEL_R::new(((self.bits >> 29) & 3) as u8) } - #[doc = "Bit 31 - Set this bit to enable clk gate"] + #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."] #[inline(always)] pub fn clk_en(&self) -> CLK_EN_R { CLK_EN_R::new(((self.bits >> 31) & 1) != 0) @@ -180,7 +180,7 @@ impl W { pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W { LCD_CLK_SEL_W::new(self, 29) } - #[doc = "Bit 31 - Set this bit to enable clk gate"] + #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."] #[inline(always)] #[must_use] pub fn clk_en(&mut self) -> CLK_EN_W { diff --git a/esp32s3/src/lcd_cam/lcd_user.rs b/esp32s3/src/lcd_cam/lcd_user.rs index edaf17b518..1c8b03899c 100644 --- a/esp32s3/src/lcd_cam/lcd_user.rs +++ b/esp32s3/src/lcd_cam/lcd_user.rs @@ -2,17 +2,17 @@ pub type R = crate::R; #[doc = "Register `LCD_USER` writer"] pub type W = crate::W; -#[doc = "Field `LCD_DOUT_CYCLELEN` reader - The output data cycles minus 1 of LCD module."] +#[doc = "Field `LCD_DOUT_CYCLELEN` reader - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."] pub type LCD_DOUT_CYCLELEN_R = crate::FieldReader; -#[doc = "Field `LCD_DOUT_CYCLELEN` writer - The output data cycles minus 1 of LCD module."] +#[doc = "Field `LCD_DOUT_CYCLELEN` writer - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."] pub type LCD_DOUT_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; -#[doc = "Field `LCD_ALWAYS_OUT_EN` reader - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] +#[doc = "Field `LCD_ALWAYS_OUT_EN` reader - LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set."] pub type LCD_ALWAYS_OUT_EN_R = crate::BitReader; -#[doc = "Field `LCD_ALWAYS_OUT_EN` writer - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] +#[doc = "Field `LCD_ALWAYS_OUT_EN` writer - LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set."] pub type LCD_ALWAYS_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LCD_8BITS_ORDER` reader - 1: invert every two data byte, valid in 1 byte mode. 0: Not change."] +#[doc = "Field `LCD_8BITS_ORDER` reader - 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap."] pub type LCD_8BITS_ORDER_R = crate::BitReader; -#[doc = "Field `LCD_8BITS_ORDER` writer - 1: invert every two data byte, valid in 1 byte mode. 0: Not change."] +#[doc = "Field `LCD_8BITS_ORDER` writer - 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap."] pub type LCD_8BITS_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `LCD_UPDATE` reader - 1: Update LCD registers, will be cleared by hardware. 0 : Not care."] pub type LCD_UPDATE_R = crate::BitReader; @@ -22,13 +22,13 @@ pub type LCD_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type LCD_BIT_ORDER_R = crate::BitReader; #[doc = "Field `LCD_BIT_ORDER` writer - 1: Change data bit order, change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] pub type LCD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LCD_BYTE_ORDER` reader - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +#[doc = "Field `LCD_BYTE_ORDER` reader - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert."] pub type LCD_BYTE_ORDER_R = crate::BitReader; -#[doc = "Field `LCD_BYTE_ORDER` writer - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +#[doc = "Field `LCD_BYTE_ORDER` writer - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert."] pub type LCD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LCD_2BYTE_EN` reader - 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8."] +#[doc = "Field `LCD_2BYTE_EN` reader - 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits."] pub type LCD_2BYTE_EN_R = crate::BitReader; -#[doc = "Field `LCD_2BYTE_EN` writer - 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8."] +#[doc = "Field `LCD_2BYTE_EN` writer - 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits."] pub type LCD_2BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `LCD_DOUT` reader - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."] pub type LCD_DOUT_R = crate::BitReader; @@ -46,7 +46,7 @@ pub type LCD_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; pub type LCD_START_R = crate::BitReader; #[doc = "Field `LCD_START` writer - LCD start sending data enable signal, valid in high level."] pub type LCD_START_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `LCD_RESET` writer - The value of command."] +#[doc = "Field `LCD_RESET` writer - Reset LCD module."] pub type LCD_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `LCD_DUMMY_CYCLELEN` reader - The dummy cycle length minus 1."] pub type LCD_DUMMY_CYCLELEN_R = crate::FieldReader; @@ -57,17 +57,17 @@ pub type LCD_CMD_2_CYCLE_EN_R = crate::BitReader; #[doc = "Field `LCD_CMD_2_CYCLE_EN` writer - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."] pub type LCD_CMD_2_CYCLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:12 - The output data cycles minus 1 of LCD module."] + #[doc = "Bits 0:12 - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."] #[inline(always)] pub fn lcd_dout_cyclelen(&self) -> LCD_DOUT_CYCLELEN_R { LCD_DOUT_CYCLELEN_R::new((self.bits & 0x1fff) as u16) } - #[doc = "Bit 13 - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] + #[doc = "Bit 13 - LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set."] #[inline(always)] pub fn lcd_always_out_en(&self) -> LCD_ALWAYS_OUT_EN_R { LCD_ALWAYS_OUT_EN_R::new(((self.bits >> 13) & 1) != 0) } - #[doc = "Bit 19 - 1: invert every two data byte, valid in 1 byte mode. 0: Not change."] + #[doc = "Bit 19 - 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap."] #[inline(always)] pub fn lcd_8bits_order(&self) -> LCD_8BITS_ORDER_R { LCD_8BITS_ORDER_R::new(((self.bits >> 19) & 1) != 0) @@ -82,12 +82,12 @@ impl R { pub fn lcd_bit_order(&self) -> LCD_BIT_ORDER_R { LCD_BIT_ORDER_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[doc = "Bit 22 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert."] #[inline(always)] pub fn lcd_byte_order(&self) -> LCD_BYTE_ORDER_R { LCD_BYTE_ORDER_R::new(((self.bits >> 22) & 1) != 0) } - #[doc = "Bit 23 - 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8."] + #[doc = "Bit 23 - 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits."] #[inline(always)] pub fn lcd_2byte_en(&self) -> LCD_2BYTE_EN_R { LCD_2BYTE_EN_R::new(((self.bits >> 23) & 1) != 0) @@ -174,19 +174,19 @@ impl core::fmt::Debug for crate::generic::Reg { } } impl W { - #[doc = "Bits 0:12 - The output data cycles minus 1 of LCD module."] + #[doc = "Bits 0:12 - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."] #[inline(always)] #[must_use] pub fn lcd_dout_cyclelen(&mut self) -> LCD_DOUT_CYCLELEN_W { LCD_DOUT_CYCLELEN_W::new(self, 0) } - #[doc = "Bit 13 - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] + #[doc = "Bit 13 - LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set."] #[inline(always)] #[must_use] pub fn lcd_always_out_en(&mut self) -> LCD_ALWAYS_OUT_EN_W { LCD_ALWAYS_OUT_EN_W::new(self, 13) } - #[doc = "Bit 19 - 1: invert every two data byte, valid in 1 byte mode. 0: Not change."] + #[doc = "Bit 19 - 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap."] #[inline(always)] #[must_use] pub fn lcd_8bits_order(&mut self) -> LCD_8BITS_ORDER_W { @@ -204,13 +204,13 @@ impl W { pub fn lcd_bit_order(&mut self) -> LCD_BIT_ORDER_W { LCD_BIT_ORDER_W::new(self, 21) } - #[doc = "Bit 22 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[doc = "Bit 22 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert."] #[inline(always)] #[must_use] pub fn lcd_byte_order(&mut self) -> LCD_BYTE_ORDER_W { LCD_BYTE_ORDER_W::new(self, 22) } - #[doc = "Bit 23 - 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8."] + #[doc = "Bit 23 - 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits."] #[inline(always)] #[must_use] pub fn lcd_2byte_en(&mut self) -> LCD_2BYTE_EN_W { @@ -240,7 +240,7 @@ impl W { pub fn lcd_start(&mut self) -> LCD_START_W { LCD_START_W::new(self, 27) } - #[doc = "Bit 28 - The value of command."] + #[doc = "Bit 28 - Reset LCD module."] #[inline(always)] #[must_use] pub fn lcd_reset(&mut self) -> LCD_RESET_W { diff --git a/esp32s3/svd/patches/esp32s3.yaml b/esp32s3/svd/patches/esp32s3.yaml index d23f11c91c..ebc56269cc 100644 --- a/esp32s3/svd/patches/esp32s3.yaml +++ b/esp32s3/svd/patches/esp32s3.yaml @@ -52,6 +52,47 @@ HMAC: dimIncrement: 0x4 size: 0x20 +LCD_CAM: + LCD_CLOCK: + _modify: + CLK_EN: + description: "Set this bit to force enable the clock for all configuration registers. Clock gate is not used." + + CAM_CTRL: + _modify: + CAM_BYTE_ORDER: + description: "1: Invert data byte order, only valid in 16-bit mode. 0: Do not change." + CAM_BIT_ORDER: + description: "1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change." + + CAM_CTRL1: + _modify: + CAM_REC_DATA_BYTELEN: + description: "Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered." + CAM_LINE_INT_NUM: + description: "Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered." + CAM_2BYTE_EN: + description: "1: The width of input data is 16 bits. 0: The width of input data is 8 bits." + CAM_AFIFO_RESET: + description: "Camera Async Rx FIFO reset signal." + + LCD_USER: + _modify: + LCD_DOUT_CYCLELEN: + description: "Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1." + LCD_ALWAYS_OUT_EN: + description: "LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set." + LCD_8BITS_ORDER: + description: "1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap." + LCD_BYTE_ORDER: + description: "1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert." + LCD_2BYTE_EN: + description: "1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits." + LCD_RESET: + description: "Reset LCD module." + LCD_DUMMY_CYCLEEN: + description: "Configure DUMMY cycles. DUMMY cycles = this value + 1." + RSA: _modify: "M_MEM*":