From 81c9ac632ead5c233728725179ed2530c2c820ec Mon Sep 17 00:00:00 2001
From: Andrzej Ratajewski <andrzej.ratajewski@intel.com>
Date: Tue, 7 Mar 2023 13:51:36 +0100
Subject: [PATCH] Fix mangling of opcodes from SPV_KHR_bit_instructions in
 SPV-IR (#1869)

---
 lib/SPIRV/SPIRVUtil.cpp                                   | 3 +++
 .../SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.cl   | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/lib/SPIRV/SPIRVUtil.cpp b/lib/SPIRV/SPIRVUtil.cpp
index e561213998..d826fedbf1 100644
--- a/lib/SPIRV/SPIRVUtil.cpp
+++ b/lib/SPIRV/SPIRVUtil.cpp
@@ -2224,6 +2224,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpGroupNonUniformBallotFindMSB:
       addUnsignedArg(1);
       break;
+    case OpBitFieldSExtract:
     case OpGroupNonUniformBallotBitExtract:
       addUnsignedArg(1);
       addUnsignedArg(2);
@@ -2244,6 +2245,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpGroupNonUniformLogicalXor:
       addUnsignedArg(3);
       break;
+    case OpBitFieldInsert:
     case OpGroupNonUniformUMax:
     case OpGroupNonUniformUMin:
       addUnsignedArg(2);
@@ -2294,6 +2296,7 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
     case OpSubgroupAvcImeSetSingleReferenceINTEL:
       addUnsignedArg(1);
       break;
+    case OpBitFieldUExtract:
     case OpSubgroupAvcImeInitializeINTEL:
     case OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL:
     case OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL:
diff --git a/test/extensions/KHR/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.cl b/test/extensions/KHR/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.cl
index 62f117642c..aad0154b09 100644
--- a/test/extensions/KHR/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.cl
+++ b/test/extensions/KHR/SPV_KHR_bit_instructions/cl_khr_extended_bit_ops.cl
@@ -3,12 +3,15 @@
 // RUN: llvm-spirv %t.bc --spirv-ext=+SPV_KHR_bit_instructions -o %t.spv
 // RUN: llvm-spirv -r -emit-opaque-pointers %t.spv -o %t.rev.bc
 // RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+// RUN: llvm-spirv -r --spirv-target-env=SPV-IR -emit-opaque-pointers %t.spv -o %t.rev.bc
+// RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-SPV-IR
 
 // CHECK-SPIRV: Capability BitInstructions
 // CHECK-SPIRV: Extension "SPV_KHR_bit_instructions"
 
 // CHECK-LLVM-LABEL: @testInsert
 // CHECK-LLVM: call spir_func <2 x i32> @_Z15bitfield_insertDv2_iS_jj(
+// CHECK-SPV-IR: call spir_func <2 x i32> @_Z22__spirv_BitFieldInsertDv2_iS_jj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[insins:[0-9]+]]
@@ -20,6 +23,8 @@ kernel void testInsert(int2 b, int2 i, global int2 *res) {
 // CHECK-LLVM-LABEL: @testExtractS
 // CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
 // CHECK-LLVM: call spir_func i16 @_Z23bitfield_extract_signedsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
+// CHECK-SPV-IR: call spir_func i16 @_Z24__spirv_BitFieldSExtractsjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[sextrbaseu:[0-9]+]]
@@ -33,6 +38,8 @@ kernel void testExtractS(short b, ushort bu, global short *res) {
 // CHECK-LLVM-LABEL: @testExtractU
 // CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
 // CHECK-LLVM: call spir_func <8 x i8> @_Z25bitfield_extract_unsignedDv8_cjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
+// CHECK-SPV-IR: call spir_func <8 x i8> @_Z24__spirv_BitFieldUExtractDv8_hjj(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbase:[0-9]+]]
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[uextrbaseu:[0-9]+]]
@@ -45,6 +52,7 @@ kernel void testExtractU(char8 b, uchar8 bu, global uchar8 *res) {
 
 // CHECK-LLVM-LABEL: @testBitReverse
 // CHECK-LLVM: call <4 x i64> @llvm.bitreverse.v4i64(
+// CHECK-SPV-IR: call <4 x i64> @llvm.bitreverse.v4i64(
 // CHECK-SPIRV: Function
 // CHECK-SPIRV: FunctionParameter {{[0-9]+}} [[revbase:[0-9]+]]
 // CHECK-SPIRV: BitReverse {{[0-9]+}} {{[0-9]+}} [[revbase]]