From 6f80df1153d13b33caa23d7d43dd7a264d34bb6a Mon Sep 17 00:00:00 2001 From: Vlad Korovin Date: Tue, 19 Mar 2024 18:13:42 +0100 Subject: [PATCH] [Backport to 10] Support SPV_INTEL_maximum_registers extension (#2344) (#2405) --- include/LLVMSPIRVExtensions.inc | 1 + lib/SPIRV/SPIRVReader.cpp | 42 +++++++++ lib/SPIRV/SPIRVWriter.cpp | 74 ++++++++++++---- lib/SPIRV/SPIRVWriter.h | 1 + lib/SPIRV/libSPIRV/SPIRVEntry.cpp | 10 ++- lib/SPIRV/libSPIRV/SPIRVEntry.h | 88 ++++++++++++++----- lib/SPIRV/libSPIRV/SPIRVEnum.h | 6 ++ lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h | 5 +- lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 8 ++ lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h | 1 + lib/SPIRV/libSPIRV/SPIRVStream.cpp | 1 + lib/SPIRV/libSPIRV/SPIRVStream.h | 1 + lib/SPIRV/libSPIRV/spirv.hpp | 9 ++ .../registerallocmode_maxreg_extension.ll | 85 ++++++++++++++++++ 14 files changed, 288 insertions(+), 44 deletions(-) create mode 100644 test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc index 602cb158dc..97d49649bb 100644 --- a/include/LLVMSPIRVExtensions.inc +++ b/include/LLVMSPIRVExtensions.inc @@ -40,3 +40,4 @@ EXT(SPV_EXT_relaxed_printf_string_address_space) EXT(SPV_INTEL_hw_thread_queries) EXT(SPV_INTEL_split_barrier) EXT(SPV_INTEL_global_variable_decorations) +EXT(SPV_INTEL_maximum_registers) diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index 754430431c..5fadd28a84 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -3203,6 +3203,48 @@ bool SPIRVToLLVM::transMetadata() { F->setMetadata(kSPIR2MD::NumSIMD, getMDNodeStringIntVec(Context, EM->getLiterals())); } + if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersINTEL)) { + NamedMDNode *ExecModeMD = + M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode); + + SmallVector ValueVec; + ValueVec.push_back(ConstantAsMetadata::get(F)); + ValueVec.push_back( + ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode()))); + ValueVec.push_back( + ConstantAsMetadata::get(getUInt32(M, EM->getLiterals()[0]))); + ExecModeMD->addOperand(MDNode::get(*Context, ValueVec)); + } + if (auto *EM = BF->getExecutionMode(ExecutionModeMaximumRegistersIdINTEL)) { + NamedMDNode *ExecModeMD = + M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode); + + SmallVector ValueVec; + ValueVec.push_back(ConstantAsMetadata::get(F)); + ValueVec.push_back( + ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode()))); + + auto *ExecOp = BF->getModule()->getValue(EM->getLiterals()[0]); + ValueVec.push_back( + MDNode::get(*Context, ConstantAsMetadata::get(cast( + transValue(ExecOp, nullptr, nullptr))))); + ExecModeMD->addOperand(MDNode::get(*Context, ValueVec)); + } + if (auto *EM = + BF->getExecutionMode(ExecutionModeNamedMaximumRegistersINTEL)) { + NamedMDNode *ExecModeMD = + M->getOrInsertNamedMetadata(kSPIRVMD::ExecutionMode); + + SmallVector ValueVec; + ValueVec.push_back(ConstantAsMetadata::get(F)); + ValueVec.push_back( + ConstantAsMetadata::get(getUInt32(M, EM->getExecutionMode()))); + + assert(EM->getLiterals()[0] == 0 && + "Invalid named maximum number of registers"); + ValueVec.push_back(MDString::get(*Context, "AutoINTEL")); + ExecModeMD->addOperand(MDNode::get(*Context, ValueVec)); + } } return true; } diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index ff8f54d080..23d389dfb5 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -632,6 +632,9 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) { if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute)) transVectorComputeMetadata(F); + if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_maximum_registers)) + transFunctionMetadataAsExecutionMode(BF, F); + SPIRVDBG(dbgs() << "[transFunction] " << *F << " => "; spvdbgs() << *BF << '\n';) return BF; @@ -708,6 +711,38 @@ void LLVMToSPIRV::transVectorComputeMetadata(Function *F) { } } +void LLVMToSPIRV::transFunctionMetadataAsExecutionMode(SPIRVFunction *BF, + Function *F) { + SmallVector RegisterAllocModeMDs; + F->getMetadata("RegisterAllocMode", RegisterAllocModeMDs); + + for (unsigned I = 0; I < RegisterAllocModeMDs.size(); I++) { + auto *RegisterAllocMode = RegisterAllocModeMDs[I]->getOperand(0).get(); + if (isa(RegisterAllocMode)) { + const std::string Str = getMDOperandAsString(RegisterAllocModeMDs[I], 0); + const NamedMaximumNumberOfRegisters NamedValue = + SPIRVNamedMaximumNumberOfRegistersNameMap::rmap(Str); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, ExecutionModeNamedMaximumRegistersINTEL, + NamedValue))); + } else if (isa(RegisterAllocMode)) { + auto *RegisterAllocNodeMDOp = + getMDOperandAsMDNode(RegisterAllocModeMDs[I], 0); + const int Num = getMDOperandAsInt(RegisterAllocNodeMDOp, 0); + auto *Const = + BM->addConstant(transType(Type::getInt32Ty(F->getContext())), Num); + BF->addExecutionMode(BM->add(new SPIRVExecutionModeId( + BF, ExecutionModeMaximumRegistersIdINTEL, Const->getId()))); + } else { + const int64_t RegisterAllocVal = + mdconst::dyn_extract(RegisterAllocMode)->getZExtValue(); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, ExecutionModeMaximumRegistersINTEL, + RegisterAllocVal))); + } + } +} + SPIRVValue *LLVMToSPIRV::transConstant(Value *V) { if (auto CPNull = dyn_cast(V)) return BM->addNullConstant( @@ -3254,15 +3289,16 @@ bool LLVMToSPIRV::transExecutionMode() { case spv::ExecutionModeContractionOff: case spv::ExecutionModeInitializer: case spv::ExecutionModeFinalizer: - BF->addExecutionMode(BM->add( - new SPIRVExecutionMode(BF, static_cast(EMode)))); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, static_cast(EMode)))); + break; break; case spv::ExecutionModeLocalSize: case spv::ExecutionModeLocalSizeHint: { unsigned X, Y, Z; N.get(X).get(Y).get(Z); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), X, Y, Z))); + OpExecutionMode, BF, static_cast(EMode), X, Y, Z))); } break; case spv::ExecutionModeMaxWorkgroupSizeINTEL: { if (BM->isAllowedToUseExtension( @@ -3270,7 +3306,8 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned X, Y, Z; N.get(X).get(Y).get(Z); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), X, Y, Z))); + OpExecutionMode, BF, static_cast(EMode), X, Y, + Z))); BM->addCapability(CapabilityKernelAttributesINTEL); } } break; @@ -3279,8 +3316,8 @@ bool LLVMToSPIRV::transExecutionMode() { case spv::ExecutionModeSubgroupsPerWorkgroup: { unsigned X; N.get(X); - BF->addExecutionMode(BM->add( - new SPIRVExecutionMode(BF, static_cast(EMode), X))); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, static_cast(EMode), X))); } break; case spv::ExecutionModeNumSIMDWorkitemsINTEL: { if (BM->isAllowedToUseExtension( @@ -3288,7 +3325,7 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned X; N.get(X); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), X))); + OpExecutionMode, BF, static_cast(EMode), X))); BM->addCapability(CapabilityFPGAKernelAttributesINTEL); } } break; @@ -3298,7 +3335,7 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned X; N.get(X); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), X))); + OpExecutionMode, BF, static_cast(EMode), X))); BM->addCapability(CapabilityFPGAKernelAttributesINTEL); } } break; @@ -3308,15 +3345,16 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned SLMSize; N.get(SLMSize); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), SLMSize))); + OpExecutionMode, BF, static_cast(EMode), SLMSize))); } break; case spv::ExecutionModeNamedBarrierCountINTEL: { if (!BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute)) break; unsigned NBarrierCnt = 0; N.get(NBarrierCnt); - BF->addExecutionMode(new SPIRVExecutionMode( - BF, static_cast(EMode), NBarrierCnt)); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, static_cast(EMode), + NBarrierCnt))); BM->addExtension(ExtensionID::SPV_INTEL_vector_compute); BM->addCapability(CapabilityVectorComputeINTEL); } break; @@ -3331,7 +3369,8 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned TargetWidth; N.get(TargetWidth); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), TargetWidth))); + OpExecutionMode, BF, static_cast(EMode), + TargetWidth))); } break; case spv::ExecutionModeRoundingModeRTPINTEL: case spv::ExecutionModeRoundingModeRTNINTEL: @@ -3343,12 +3382,13 @@ bool LLVMToSPIRV::transExecutionMode() { unsigned TargetWidth; N.get(TargetWidth); BF->addExecutionMode(BM->add(new SPIRVExecutionMode( - BF, static_cast(EMode), TargetWidth))); + OpExecutionMode, BF, static_cast(EMode), + TargetWidth))); } break; case spv::ExecutionModeFastCompositeKernelINTEL: { if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite)) - BF->addExecutionMode(BM->add( - new SPIRVExecutionMode(BF, static_cast(EMode)))); + BF->addExecutionMode(BM->add(new SPIRVExecutionMode( + OpExecutionMode, BF, static_cast(EMode)))); } break; default: llvm_unreachable("invalid execution mode"); @@ -3393,8 +3433,8 @@ void LLVMToSPIRV::transFPContract() { } if (DisableContraction) { - BF->addExecutionMode(BF->getModule()->add( - new SPIRVExecutionMode(BF, spv::ExecutionModeContractionOff))); + BF->addExecutionMode(BF->getModule()->add(new SPIRVExecutionMode( + OpExecutionMode, BF, spv::ExecutionModeContractionOff))); } } } diff --git a/lib/SPIRV/SPIRVWriter.h b/lib/SPIRV/SPIRVWriter.h index 08b227ccfa..a247de2007 100644 --- a/lib/SPIRV/SPIRVWriter.h +++ b/lib/SPIRV/SPIRVWriter.h @@ -113,6 +113,7 @@ class LLVMToSPIRV : public ModulePass { SPIRVWord transFunctionControlMask(Function *); SPIRVFunction *transFunctionDecl(Function *F); void transVectorComputeMetadata(Function *F); + void transFunctionMetadataAsExecutionMode(SPIRVFunction *BF, Function *F); bool transGlobalVariables(); Op transBoolOpCode(SPIRVValue *Opn, Op OC); diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp index a3122d01e3..e00d98fb1f 100644 --- a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp +++ b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp @@ -540,7 +540,7 @@ SPIRVEntryPoint::SPIRVEntryPoint(SPIRVModule *TheModule, SPIRVExecutionModelKind TheExecModel, SPIRVId TheId, const std::string &TheName, std::vector Variables) - : SPIRVAnnotation(TheModule->get(TheId), + : SPIRVAnnotation(OpEntryPoint, TheModule->get(TheId), getSizeInWords(TheName) + Variables.size() + 3), ExecModel(TheExecModel), Name(TheName), Variables(Variables) {} @@ -560,7 +560,7 @@ void SPIRVExecutionMode::encode(spv_ostream &O) const { void SPIRVExecutionMode::decode(std::istream &I) { getDecoder(I) >> Target >> ExecMode; - switch (ExecMode) { + switch (static_cast(ExecMode)) { case ExecutionModeLocalSize: case ExecutionModeLocalSizeHint: case ExecutionModeMaxWorkgroupSizeINTEL: @@ -583,6 +583,9 @@ void SPIRVExecutionMode::decode(std::istream &I) { case ExecutionModeSubgroupSize: case ExecutionModeMaxWorkDimINTEL: case ExecutionModeNumSIMDWorkitemsINTEL: + case ExecutionModeMaximumRegistersINTEL: + case ExecutionModeMaximumRegistersIdINTEL: + case ExecutionModeNamedMaximumRegistersINTEL: WordLiterals.resize(1); break; default: @@ -604,7 +607,8 @@ SPIRVForward *SPIRVAnnotationGeneric::getOrCreateTarget() const { } SPIRVName::SPIRVName(const SPIRVEntry *TheTarget, const std::string &TheStr) - : SPIRVAnnotation(TheTarget, getSizeInWords(TheStr) + 2), Str(TheStr) {} + : SPIRVAnnotation(OpName, TheTarget, getSizeInWords(TheStr) + 2), + Str(TheStr) {} void SPIRVName::encode(spv_ostream &O) const { getEncoder(O) << Target << Str; } diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.h b/lib/SPIRV/libSPIRV/SPIRVEntry.h index e444d20240..ad08041b47 100644 --- a/lib/SPIRV/libSPIRV/SPIRVEntry.h +++ b/lib/SPIRV/libSPIRV/SPIRVEntry.h @@ -509,22 +509,23 @@ class SPIRVAnnotationGeneric : public SPIRVEntryNoIdGeneric { SPIRVId Target; }; -template class SPIRVAnnotation : public SPIRVAnnotationGeneric { +class SPIRVAnnotation : public SPIRVAnnotationGeneric { public: // Complete constructor - SPIRVAnnotation(const SPIRVEntry *TheTarget, unsigned TheWordCount) + SPIRVAnnotation(Op OC, const SPIRVEntry *TheTarget, unsigned TheWordCount) : SPIRVAnnotationGeneric(TheTarget->getModule(), TheWordCount, OC, TheTarget->getId()) {} - // Incomplete constructor - SPIRVAnnotation() : SPIRVAnnotationGeneric(OC) {} + // Incomplete constructors + SPIRVAnnotation(Op OC) : SPIRVAnnotationGeneric(OC) {} + SPIRVAnnotation() : SPIRVAnnotationGeneric(OpNop) {} }; -class SPIRVEntryPoint : public SPIRVAnnotation { +class SPIRVEntryPoint : public SPIRVAnnotation { public: SPIRVEntryPoint(SPIRVModule *TheModule, SPIRVExecutionModelKind, SPIRVId TheId, const std::string &TheName, std::vector Variables); - SPIRVEntryPoint() {} + SPIRVEntryPoint() : SPIRVAnnotation(OpEntryPoint) {} _SPIRV_DCL_ENCDEC protected: @@ -535,12 +536,12 @@ class SPIRVEntryPoint : public SPIRVAnnotation { std::vector Variables; }; -class SPIRVName : public SPIRVAnnotation { +class SPIRVName : public SPIRVAnnotation { public: // Complete constructor SPIRVName(const SPIRVEntry *TheTarget, const std::string &TheStr); // Incomplete constructor - SPIRVName() {} + SPIRVName() : SPIRVAnnotation(OpName) {} protected: _SPIRV_DCL_ENCDEC @@ -549,18 +550,18 @@ class SPIRVName : public SPIRVAnnotation { std::string Str; }; -class SPIRVMemberName : public SPIRVAnnotation { +class SPIRVMemberName : public SPIRVAnnotation { public: static const SPIRVWord FixedWC = 3; // Complete constructor SPIRVMemberName(const SPIRVEntry *TheTarget, SPIRVWord TheMemberNumber, const std::string &TheStr) - : SPIRVAnnotation(TheTarget, FixedWC + getSizeInWords(TheStr)), + : SPIRVAnnotation(OpName, TheTarget, FixedWC + getSizeInWords(TheStr)), MemberNumber(TheMemberNumber), Str(TheStr) { validate(); } // Incomplete constructor - SPIRVMemberName() : MemberNumber(SPIRVWORD_MAX) {} + SPIRVMemberName() : SPIRVAnnotation(OpName), MemberNumber(SPIRVWORD_MAX) {} protected: _SPIRV_DCL_ENCDEC @@ -636,31 +637,33 @@ class SPIRVLine : public SPIRVEntry { SPIRVWord Column; }; -class SPIRVExecutionMode : public SPIRVAnnotation { +class SPIRVExecutionMode : public SPIRVAnnotation { public: // Complete constructor for LocalSize, LocalSizeHint - SPIRVExecutionMode(SPIRVEntry *TheTarget, SPIRVExecutionModeKind TheExecMode, - SPIRVWord X, SPIRVWord Y, SPIRVWord Z) - : SPIRVAnnotation(TheTarget, 6), ExecMode(TheExecMode) { + SPIRVExecutionMode(Op OC, SPIRVEntry *TheTarget, + SPIRVExecutionModeKind TheExecMode, SPIRVWord X, + SPIRVWord Y, SPIRVWord Z) + : SPIRVAnnotation(OC, TheTarget, 6), ExecMode(TheExecMode) { WordLiterals.push_back(X); WordLiterals.push_back(Y); WordLiterals.push_back(Z); updateModuleVersion(); } // Complete constructor for VecTypeHint, SubgroupSize, SubgroupsPerWorkgroup - SPIRVExecutionMode(SPIRVEntry *TheTarget, SPIRVExecutionModeKind TheExecMode, - SPIRVWord Code) - : SPIRVAnnotation(TheTarget, 4), ExecMode(TheExecMode) { + SPIRVExecutionMode(Op OC, SPIRVEntry *TheTarget, + SPIRVExecutionModeKind TheExecMode, SPIRVWord Code) + : SPIRVAnnotation(OC, TheTarget, 4), ExecMode(TheExecMode) { WordLiterals.push_back(Code); - updateModuleVersion(); } // Complete constructor for ContractionOff - SPIRVExecutionMode(SPIRVEntry *TheTarget, SPIRVExecutionModeKind TheExecMode) - : SPIRVAnnotation(TheTarget, 3), ExecMode(TheExecMode) { + SPIRVExecutionMode(Op OC, SPIRVEntry *TheTarget, + SPIRVExecutionModeKind TheExecMode) + : SPIRVAnnotation(OC, TheTarget, 3), ExecMode(TheExecMode) { updateModuleVersion(); } // Incomplete constructor - SPIRVExecutionMode() : ExecMode(ExecutionModeInvocations) {} + SPIRVExecutionMode() + : SPIRVAnnotation(OpExecutionMode), ExecMode(ExecutionModeInvocations) {} SPIRVExecutionModeKind getExecutionMode() const { return ExecMode; } const std::vector &getLiterals() const { return WordLiterals; } SPIRVCapVec getRequiredCapability() const override { @@ -680,12 +683,45 @@ class SPIRVExecutionMode : public SPIRVAnnotation { } } + SPIRVExtSet getRequiredExtensions() const override { + switch (static_cast(ExecMode)) { + case ExecutionModeMaximumRegistersINTEL: + case ExecutionModeMaximumRegistersIdINTEL: + case ExecutionModeNamedMaximumRegistersINTEL: + return getSet(ExtensionID::SPV_INTEL_maximum_registers); + default: + return SPIRVExtSet(); + } + } + protected: _SPIRV_DCL_ENCDEC SPIRVExecutionModeKind ExecMode; std::vector WordLiterals; }; +class SPIRVExecutionModeId : public SPIRVExecutionMode { +public: + // Complete constructor for LocalSizeId, LocalSizeHintId + SPIRVExecutionModeId(SPIRVEntry *TheTarget, + SPIRVExecutionModeKind TheExecMode, SPIRVWord X, + SPIRVWord Y, SPIRVWord Z) + : SPIRVExecutionMode(OpExecutionModeId, TheTarget, TheExecMode, X, Y, Z) { + updateModuleVersion(); + } + // Complete constructor for SubgroupsPerWorkgroupId + SPIRVExecutionModeId(SPIRVEntry *TheTarget, + SPIRVExecutionModeKind TheExecMode, SPIRVWord Code) + : SPIRVExecutionMode(OpExecutionModeId, TheTarget, TheExecMode, Code) { + updateModuleVersion(); + } + // Incomplete constructor + SPIRVExecutionModeId() : SPIRVExecutionMode() {} + SPIRVWord getRequiredSPIRVVersion() const override { + return static_cast(VersionNumber::SPIRV_1_2); + } +}; + class SPIRVComponentExecutionModes { typedef std::multimap SPIRVExecutionModeMap; @@ -719,6 +755,11 @@ class SPIRVComponentExecutionModes { return IsDenorm(EMK) || IsRoundingMode(EMK) || IsFPMode(EMK) || IsOtherFP(EMK); }; + auto IsMaxRegisters = [&](auto EMK) { + return EMK == ExecutionModeMaximumRegistersINTEL || + EMK == ExecutionModeMaximumRegistersIdINTEL || + EMK == ExecutionModeNamedMaximumRegistersINTEL; + }; auto IsCompatible = [&](SPIRVExecutionMode *EM0, SPIRVExecutionMode *EM1) { if (EM0->getTargetId() != EM1->getTargetId()) return true; @@ -732,7 +773,8 @@ class SPIRVComponentExecutionModes { return true; return !(IsDenorm(EMK0) && IsDenorm(EMK1)) && !(IsRoundingMode(EMK0) && IsRoundingMode(EMK1)) && - !(IsFPMode(EMK0) && IsFPMode(EMK1)); + !(IsFPMode(EMK0) && IsFPMode(EMK1)) && + !(IsMaxRegisters(EMK0) && IsMaxRegisters(EMK1)); }; for (auto I = ExecModes.begin(); I != ExecModes.end(); ++I) { assert(IsCompatible(ExecMode, (*I).second) && diff --git a/lib/SPIRV/libSPIRV/SPIRVEnum.h b/lib/SPIRV/libSPIRV/SPIRVEnum.h index 8a5b6222c6..54e0203178 100644 --- a/lib/SPIRV/libSPIRV/SPIRVEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVEnum.h @@ -260,6 +260,12 @@ template <> inline void SPIRVMap::init() { {CapabilityFastCompositeINTEL}); ADD_VEC_INIT(ExecutionModeNamedBarrierCountINTEL, {CapabilityVectorComputeINTEL}); + ADD_VEC_INIT(ExecutionModeMaximumRegistersINTEL, + {CapabilityRegisterLimitsINTEL}); + ADD_VEC_INIT(ExecutionModeMaximumRegistersIdINTEL, + {CapabilityRegisterLimitsINTEL}); + ADD_VEC_INIT(ExecutionModeNamedMaximumRegistersINTEL, + {CapabilityRegisterLimitsINTEL}); } template <> inline void SPIRVMap::init() { diff --git a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h index b4a3b392ef..0c28fa948c 100644 --- a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h @@ -68,7 +68,7 @@ inline bool isValid(spv::SourceLanguage V) { } inline bool isValid(spv::ExecutionModel V) { - switch (V) { + switch (static_cast(V)) { case ExecutionModelVertex: case ExecutionModelTessellationControl: case ExecutionModelTessellationEvaluation: @@ -76,6 +76,9 @@ inline bool isValid(spv::ExecutionModel V) { case ExecutionModelFragment: case ExecutionModelGLCompute: case ExecutionModelKernel: + case ExecutionModeMaximumRegistersINTEL: + case ExecutionModeMaximumRegistersIdINTEL: + case ExecutionModeNamedMaximumRegistersINTEL: return true; default: return false; diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index e827d10a48..ae51500a7f 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -577,6 +577,7 @@ template <> inline void SPIRVMap::init() { add(CapabilityGroupNonUniformClustered, "GroupNonUniformClustered"); add(CapabilityFunctionFloatControlINTEL, "FunctionFloatControlINTEL"); add(CapabilityLongConstantCompositeINTEL, "LongConstantCompositeINTEL"); + add(CapabilityRegisterLimitsINTEL, "RegisterLimitsINTEL"); add(CapabilityFastCompositeINTEL, "FastCompositeINTEL"); add(CapabilityOptNoneINTEL, "OptNoneINTEL"); add(CapabilityArbitraryPrecisionIntegersINTEL, @@ -597,6 +598,13 @@ template <> inline void SPIRVMap::init() { } SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap) +template <> +inline void SPIRVMap::init() { + add(NamedMaximumNumberOfRegistersAutoINTEL, "AutoINTEL"); +} +SPIRV_DEF_NAMEMAP(NamedMaximumNumberOfRegisters, + SPIRVNamedMaximumNumberOfRegistersNameMap); + } /* namespace SPIRV */ #endif // SPIRV_LIBSPIRV_SPIRVNAMEMAPENUM_H diff --git a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h index 4c092c6e2f..8b96d7bb72 100644 --- a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h @@ -295,6 +295,7 @@ _SPIRV_OP(TypePipeStorage, 322) _SPIRV_OP(ConstantPipeStorage, 323) _SPIRV_OP(CreatePipeFromPipeStorage, 324) _SPIRV_OP(ModuleProcessed, 330) +_SPIRV_OP(ExecutionModeId, 331) _SPIRV_OP(DecorateId, 332) _SPIRV_OP(GroupNonUniformElect, 333) _SPIRV_OP(GroupNonUniformAll, 334) diff --git a/lib/SPIRV/libSPIRV/SPIRVStream.cpp b/lib/SPIRV/libSPIRV/SPIRVStream.cpp index eaf1d9e955..3f4a4a8035 100644 --- a/lib/SPIRV/libSPIRV/SPIRVStream.cpp +++ b/lib/SPIRV/libSPIRV/SPIRVStream.cpp @@ -134,6 +134,7 @@ SPIRV_DEF_ENCDEC(Capability) SPIRV_DEF_ENCDEC(Decoration) SPIRV_DEF_ENCDEC(OCLExtOpKind) SPIRV_DEF_ENCDEC(SPIRVDebugExtOpKind) +SPIRV_DEF_ENCDEC(NamedMaximumNumberOfRegisters) SPIRV_DEF_ENCDEC(LinkageType) // Read a string with padded 0's at the end so that they form a stream of diff --git a/lib/SPIRV/libSPIRV/SPIRVStream.h b/lib/SPIRV/libSPIRV/SPIRVStream.h index f8b823e995..e811cbe26f 100644 --- a/lib/SPIRV/libSPIRV/SPIRVStream.h +++ b/lib/SPIRV/libSPIRV/SPIRVStream.h @@ -226,6 +226,7 @@ SPIRV_DEC_ENCDEC(Capability) SPIRV_DEC_ENCDEC(Decoration) SPIRV_DEC_ENCDEC(OCLExtOpKind) SPIRV_DEC_ENCDEC(SPIRVDebugExtOpKind) +SPIRV_DEC_ENCDEC(NamedMaximumNumberOfRegisters) SPIRV_DEC_ENCDEC(LinkageType) const SPIRVEncoder &operator<<(const SPIRVEncoder &O, const std::string &Str); diff --git a/lib/SPIRV/libSPIRV/spirv.hpp b/lib/SPIRV/libSPIRV/spirv.hpp index 2cadec7d1c..51cab3f91c 100644 --- a/lib/SPIRV/libSPIRV/spirv.hpp +++ b/lib/SPIRV/libSPIRV/spirv.hpp @@ -174,6 +174,9 @@ enum ExecutionMode { ExecutionModeNumSIMDWorkitemsINTEL = 5896, ExecutionModeFastCompositeKernelINTEL = 6088, ExecutionModeNamedBarrierCountINTEL = 6417, + ExecutionModeMaximumRegistersINTEL = 6461, + ExecutionModeMaximumRegistersIdINTEL = 6462, + ExecutionModeNamedMaximumRegistersINTEL = 6463, ExecutionModeMax = 0x7fffffff, }; @@ -985,6 +988,7 @@ enum Capability { CapabilityFastCompositeINTEL = 6093, CapabilityOptNoneINTEL = 6094, CapabilitySplitBarrierINTEL = 6141, + CapabilityRegisterLimitsINTEL = 6460, CapabilityMax = 0x7fffffff, }; @@ -993,6 +997,11 @@ enum PackedVectorFormat { PackedVectorFormatMax = 0x7fffffff, }; +enum NamedMaximumNumberOfRegisters { + NamedMaximumNumberOfRegistersAutoINTEL = 0, + NamedMaximumNumberOfRegistersMax = 0x7fffffff, +}; + enum Op { OpNop = 0, OpUndef = 1, diff --git a/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll b/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll new file mode 100644 index 0000000000..471e257442 --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_maximum_registers/registerallocmode_maxreg_extension.ll @@ -0,0 +1,85 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv -spirv-text --spirv-ext=+SPV_INTEL_maximum_registers %t.bc +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_maximum_registers -o %t.spv +; RUN: llvm-spirv -r %t.spv -spirv-target-env=SPV-IR -o - | llvm-dis -o %t.rev.ll +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC0:]] "main_l3" +; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC1:]] "main_l6" +; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC2:]] "main_l9" +; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC3:]] "main_l13" +; CHECK-SPIRV: EntryPoint [[#]] [[#FUNC4:]] "main_l19" + +; CHECK-SPIRV: ExecutionMode [[#FUNC0]] 6461 2 +; CHECK-SPIRV: ExecutionMode [[#FUNC1]] 6461 1 +; CHECK-SPIRV: ExecutionMode [[#FUNC2]] 6463 0 +; CHECK-SPIRV: ExecutionModeId [[#FUNC3]] 6462 [[#Const3:]] +; CHECK-SPIRV: TypeInt [[#TypeInt:]] 32 0 +; CHECK-SPIRV: Constant [[#TypeInt]] [[#Const3]] 3 + +; CHECK-SPIRV-NOT: ExecutionMode [[#FUNC4]] + +; CHECK-LLVM: !spirv.ExecutionMode = !{![[#FLAG0:]], ![[#FLAG1:]], ![[#FLAG2:]], ![[#FLAG3:]]} +; CHECK-LLVM: ![[#FLAG0]] = !{void ()* @main_l3, i32 6461, i32 2} +; CHECK-LLVM: ![[#FLAG1]] = !{void ()* @main_l6, i32 6461, i32 1} +; CHECK-LLVM: ![[#FLAG2]] = !{void ()* @main_l9, i32 6463, !"AutoINTEL"} +; CHECK-LLVM: ![[#FLAG3]] = !{void ()* @main_l13, i32 6462, ![[#VAL:]]} +; CHECK-LLVM: ![[#VAL]] = !{i32 3} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir64" + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l3() #0 !RegisterAllocMode !10 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l6() #0 !RegisterAllocMode !11 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l9() #0 !RegisterAllocMode !12 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l13() #0 !RegisterAllocMode !13 { +newFuncRoot: + ret void +} + +; Function Attrs: noinline nounwind optnone +define weak dso_local spir_kernel void @main_l19() #0 { +newFuncRoot: + ret void +} + +attributes #0 = { noinline nounwind optnone } + + +!opencl.compiler.options = !{!0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0} +!spirv.Source = !{!2, !3, !3, !3, !3, !3, !2, !3, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2, !2} +!llvm.module.flags = !{!4, !5, !6, !7, !8} +!spirv.MemoryModel = !{!9, !9, !9, !9, !9, !9} +!spirv.ExecutionMode = !{} + +!0 = !{} +!2 = !{i32 4, i32 200000} +!3 = !{i32 3, i32 200000} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 7, !"openmp", i32 50} +!6 = !{i32 7, !"openmp-device", i32 50} +!7 = !{i32 1, !"PIC Level", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{i32 2, i32 2} +!10 = !{i32 2} +!11 = !{i32 1} +!12 = !{!"AutoINTEL"} +!13 = !{!14} +!14 = !{i32 3}