+
+ +
+

Register FIFO

+
+
+ENTITY REG_FIFO IS
+

This component is the most primitive FIFO here which is made of registers that buffers data also when the +output TX_DST_RDY is deasserted. In that case, the buffer keeps an output RX_DST_RDY asserted +unless the FIFO is full. If the TX_DST_RDY is asserted, the buffer behaves as a set of register +stages of the size ITEMS.

+
+

Warning

+

It is advised to use this component only on a very limited amounts of DATA_WIDTH*ITEMS. +Otherwise the consumption of the registers can be huge. For more items, refer to other types +of FIFO.

+
+Generics + + + + + + + + + + + + + + + + + + + + + + + + +

Generic

Type

Default

Description

DATA_WIDTH

natural

256

Bit width of data

ITEMS

natural

2

FAKE_FIFO

boolean

FALSE)

If this is true, the input data are directly connected to the output as well as the +handshaking signals.

+Ports + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Port

Type

Mode

Description

CLK

std_logic

in

RST

std_logic

in

RX_DATA

std_logic_vector(DATA_WIDTH-1 downto 0)

in

RX_SRC_RDY

std_logic

in

RX_DST_RDY

std_logic

out

TX_DATA

std_logic_vector(DATA_WIDTH -1 downto 0)

out

TX_SRC_RDY

std_logic

out

TX_DST_RDY

std_logic)

in

+
+ +
+ + +
+